Stacked Semiconductor Device Power Distribution via Loop Wiring
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Solution Overview
Problem
The existing stacked semiconductor devices experience a significant voltage drop as the number of semiconductor chips increases, leading to a decrease in the power source voltage applied to internal circuits, particularly in face-up stacked configurations, where the power supply voltage needs to traverse multiple resistance components, resulting in inadequate voltage levels for operation.
Innovation Solution
The solution involves a stacked semiconductor device configuration where power is supplied from multiple directions using an interposer substrate, intermediate interposer substrates, and a cap substrate, with bonding wires or bypass conductors to create a loop structure for power supply wiring, reducing resistance and voltage drop, and ensuring power is applied from both the bottom and top layers, as well as intermediate layers, to maintain sufficient voltage across all chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked in a face-up configuration to increase storage density, then the storage capacity is improved, but the voltage drop increases due to multiple resistance components in series
Solution Approach 1:
The patent transitions from a single-direction power supply (bottom-up only) to multi-directional power supply by adding power supply paths from intermediate layers and top layer. This dimensional change in power distribution architecture reduces the effective resistance path length and provides parallel current paths, thereby reducing voltage drop while maintaining the stacked configuration for high storage density.
Solution Approach 2:
The patent divides the power supply function into multiple segments: bottom layer power supply terminals, intermediate layer power supply terminals, and top layer power supply terminals. Each segment independently supplies power to adjacent chips, creating multiple parallel current paths that reduce the total resistance and voltage drop across the stacked structure.
2Quantity of substance
If more semiconductor chips are stacked to increase capacity, then the storage capacity is improved, but the power source voltage applied to internal circuits decreases
Solution Approach 1:
The patent adds vertical power supply dimensions by introducing intermediate and top power supply terminals, creating a three-dimensional power distribution network. This allows power to be supplied from multiple heights in the stack, reducing the voltage drop accumulation that occurs in single-direction power supply and maintaining adequate power source voltage for internal circuits even in high-capacity multi-chip configurations.
Solution Approach 2:
The patent incorporates intermediate power supply terminals within the stack structure that proactively supply power to upper chips before the voltage can drop to inadequate levels. This preliminary power injection at intermediate stages prevents the cumulative voltage drop that would otherwise occur in long series resistance paths.
3Loss of energy
If the number of through electrodes is increased to reduce resistance, then the voltage drop is reduced, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the power supply function across multiple layers, with each layer having its own power supply terminals. This segmentation allows each through electrode to serve a limited vertical range (adjacent chips only), reducing the required current capacity per electrode and enabling the use of simpler, lower-resistance materials without requiring an excessive number of electrodes throughout the entire stack.
Solution Approach 2:
The patent adds the dimension of intermediate power supply locations, transforming the power distribution from a single bottom-up path to a multi-level network. This dimensional addition creates parallel power paths at different heights, reducing the effective resistance without requiring a proportional increase in the number of through electrodes, as each electrode serves a localized vertical segment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses voltage drops, ensuring that the power source voltage is maintained at or above the minimum operable level for DRAMs, even with multiple stacked layers, by distributing the power supply across multiple paths, thereby enhancing the reliability and efficiency of the semiconductor device.
Implementation Method 1
power supply wiring arranged in a loop structure... bonding wires or bypass conductors to create a loop structure for power supply wiring, reducing resistance and voltage drop
Data Source
AI summary
A stacked semiconductor device includes an interposer substrate having external power supply terminals, and semiconductor chips stacked on the interposer substrate. A power supply wiring arranged in the semiconductor chip located in the bottom layer is connected to the external power supply terminal via a bump electrode, the power supply wiring arranged in the semiconductor chip located in the top layer is connected to the external power supply terminal via a bonding wire, and the power supply wirings each arranged in adjacent semiconductor chips are mutually connected via the through electrode. Such a loop structure can solve a problem such that the higher the semiconductor chip, the larger its voltage drop.