3D Stacked Semiconductor Transistors for Low-Leakage Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Electronic devices, particularly those utilizing semiconductor devices, face issues with increased leakage current in high-temperature environments, leading to potential malfunctions, and require high portability, small size, and efficient power consumption while supporting multiple functionalities such as power supply, signal processing, and memory operations.
Innovation Solution
A semiconductor device is designed with multiple layers, including transistors with different semiconductor materials (Si, Ga, In, Zn) stacked on a substrate, utilizing a crystal growth process to form overlapping transistors and incorporating an oxide semiconductor (OS) transistor with a back gate for stable operation and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple devices (power supply control unit, signal processing control unit, arithmetic processing unit, memory device) are integrated to support multiple functionalities, then the functionality and versatility of the electronic device is improved, but the size of the electronic device increases
Solution Approach 1:
The patent applies three-dimensional stacking of transistor layers to integrate multiple functional units vertically. Different semiconductor materials (Si, Ga, In, Zn) are stacked in multiple layers to form power supply control units, signal processing units, arithmetic units, and memory devices in the vertical dimension, enabling high-functionality integration without increasing planar device size.
Solution Approach 2:
The patent implements nested integration where transistor layers are stacked within a compact vertical structure. Each semiconductor layer (first through fourth layers) contains transistors that are nested vertically, with overlapping source/drain regions between layers, creating a space-efficient nested configuration that maximizes functionality within minimal volume.
2Speed
If communication speed is increased for 5G compatibility, then the transmission speed and data handling capability is improved, but heat generation and leakage current increase causing potential malfunctions
Solution Approach 1:
The patent employs composite semiconductor structures combining multiple materials (Si, Ga, In, Zn) in stacked layers. Each material contributes different electrical characteristics, with oxide semiconductor layers providing low leakage current properties that ensure stable operation even at high communication speeds required for 5G compatibility.
Solution Approach 2:
The patent applies different semiconductor materials to specific functional regions and layers based on their local requirements. Oxide semiconductors are used in regions requiring low leakage current for stability, while other materials are used where high-speed performance is prioritized, creating localized optimization throughout the device structure.
3Reliability
If oxide semiconductor transistor with back gate is used, then the operation stability and leakage current control is improved, but the device complexity and manufacturing process complexity increases
Solution Approach 1:
The patent segments the semiconductor device into distinct functional layers, with oxide semiconductor transistors forming specific segments (first through fourth layers) with controlled thicknesses (5 nm to 50 nm). The back gate structure is implemented as a separate controllable element, allowing independent optimization of channel control without complicating the overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a semiconductor device with stable operation, low power consumption, high reliability, and high productivity, enabling small form factor and efficient integration of multiple functionalities.
Implementation Method 1
a crystal growth process to form overlapping transistors
Data Source
AI summary
A small-size semiconductor device is provided. The semiconductor device includes a first layer, a second layer, and a third layer formed over a substrate. A first transistor included in the first layer includes a first semiconductor layer containing Si. A second transistor included in the second layer includes a second semiconductor layer containing Ga. A third transistor included in the third layer includes a third semiconductor layer containing at least one of In and Zn. The first semiconductor layer of the first transistor is formed using the substrate. The second semiconductor layer of the second transistor is formed using a crystal obtained by crystal growth over the substrate. The third semiconductor layer of the third transistor is formed above the first semiconductor layer and the second semiconductor layer.