Semiconductor device, memory device, and method for forming transistor on substrate
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Solution Overview
Problem
The performance of CMOS transistors in semiconductor memory devices deteriorates during manufacturing, leading to issues such as increased resistance at interfaces, etching residue formation, and reduced yield due to phosphorus diffusion and abnormal oxidation, which affects the reliability and integration of three-dimensional stacked non-volatile memory devices.
Innovation Solution
A semiconductor device with a three-layer stacked semiconductor structure, comprising a phosphorus-doped polycrystalline semiconductor first layer, a carbon-doped polycrystalline semiconductor second layer, and a phosphorus-doped or undoped polycrystalline semiconductor third layer, where the third layer has a lower phosphorus content to prevent etching residue and oxidation, and a TSI layer is used to prevent impurity diffusion, improving the interface resistance and manufacturing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phosphorus doping is used to improve electrical conductivity in the semiconductor layer, then electrical performance is improved, but phosphorus diffusion and segregation occur causing etching residue and performance deterioration
Solution Approach 1:
A carbon-doped polycrystalline semiconductor layer is introduced as an intermediary barrier layer between phosphorus-doped regions. This carbon-doped layer prevents phosphorus diffusion and segregation during manufacturing processes, thereby eliminating etching residue while maintaining the electrical performance benefits of phosphorus doping in the adjacent layers.
Solution Approach 2:
The semiconductor structure is divided into multiple functional layers with distinct doping profiles. Instead of uniform phosphorus doping, the invention segments the structure into phosphorus-doped regions for electrical conductivity and carbon-doped regions as diffusion barriers, allowing each layer to perform its specific function without interfering with the other.
2Productivity
If three-dimensional stacked structure is implemented to increase integration, then device density is improved, but interface resistance increases affecting transistor performance
Solution Approach 1:
The invention applies different doping characteristics to different layers within the stacked structure. Each interface region is optimized with appropriate doping concentrations and types (phosphorus for conductivity, carbon for barrier properties), ensuring that local interface quality maintains low resistance while the overall three-dimensional structure achieves high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances transistor performance by preventing etching residue and phosphorus segregation, reducing defects and increasing the yield of CMOS transistors, thereby improving the reliability and integration of three-dimensional stacked non-volatile memory devices.
Implementation Method 1
a carbon-doped polycrystalline semiconductor second layer... to prevent etching residue and phosphorus segregation
Implementation Method 2
a first layer formed on the gate insulating layer and including a phosphorus-doped polycrystalline semiconductor... a third layer formed on the second layer and including a phosphorus-doped or undoped polycrystalline semiconductor
Implementation Method 3
a TSI layer is used to prevent impurity diffusion
Data Source
AI summary
A semiconductor device includes a substrate, a gate insulating layer on the substrate, and a stacked semiconductor layer. The stacked semiconductor layer includes a first layer formed on the gate insulating layer and including a phosphorus-doped polycrystalline semiconductor, a second layer formed on the first layer and including a carbon-doped polycrystalline semiconductor, and a third layer formed on the second layer and including a phosphorus-doped or undoped polycrystalline semiconductor. The semiconductor device further includes a metal layer on or above the stacked semiconductor layer. The third layer includes less phosphorus than the first layer or does not include phosphorus.