Stacked Semiconductor Memory Device With Interposer Chip
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Solution Overview
Problem
Conventional magnetic disk devices are prone to malfunction and failure under physical impact due to movable components, limiting their downsizing potential and suitability for portable devices, while semiconductor memory devices offer a promising alternative with high impact resistance and smaller form factors.
Innovation Solution
A semiconductor memory device configuration featuring a wiring board with stacked semiconductor memory chips, an interposer chip, and a semiconductor controller chip, where electrode pads on the chips are electrically connected via wires, allowing for a compact design that reduces wire length and prevents electrical shorts, while also enabling independent control and heat dissipation of each chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If magnetic disk devices are used for high recording reliability and low bit cost, then recording reliability is improved, but device size increases and physical impact resistance decreases
Solution Approach 1:
The patent replaces the mechanical magnetic disk device with a semiconductor memory device that has no moving parts. The semiconductor memory device uses electronic storage instead of magnetic recording, eliminating mechanical components like the magnetic disk and magnetic head. This substitution achieves high impact resistance and downsizing while maintaining data storage functionality.
2Reliability
If magnetic disk devices are used for high recording reliability, then reliability is improved, but physical impact resistance decreases due to movable portions
Solution Approach 1:
The patent eliminates mechanical components by replacing the magnetic disk device with a semiconductor memory device. The semiconductor memory device has no movable parts, making it resistant to physical impact. This mechanical-to-electronic substitution resolves the contradiction between reliability and impact resistance.
3Ease of manufacture
If semiconductor memory chips are arranged in parallel on a wiring board, then ease of manufacture is improved, but wire length increases causing electrical shorts and heat issues
Solution Approach 1:
The patent transitions from a two-dimensional parallel arrangement of semiconductor memory chips on a wiring board to a three-dimensional stacked arrangement. By stacking chips vertically, the wire length is significantly reduced as connections are made within the stack rather than across the board. This dimensional change resolves the contradiction between ease of manufacture and wire length.
Solution Approach 2:
The patent implements a stacked configuration where semiconductor memory chips are nested vertically one on top of another. The interposer chip is positioned between the wiring board and the memory chips, creating a nested structure that reduces the horizontal distance for electrical connections. This nesting approach minimizes wire length while maintaining manufacturability.
4Reliability
If wire length is reduced in stacked chip configuration, then electrical shorts are prevented, but device complexity increases due to stacking structure
Solution Approach 1:
The patent introduces an interposer chip as an intermediary component between the wiring board and the stacked semiconductor memory chips. The interposer chip provides a standardized interface and simplifies the connection architecture, making the complex stacked configuration more manageable. This intermediary element reduces the overall device complexity while maintaining the benefits of short wire lengths and reduced electrical shorts.
Data Source
AI summary
A plurality of semiconductor memory chips are stacked on a first main surface of a wiring board, and an interposer chip is stacked on the plurality of semiconductor chips, and a semiconductor controller chip is stacked on the interposer chip. The plurality of semiconductor memory chips are independently and electrically connected with inner connecting terminals formed on the wiring board, respectively, and independently controlled by the semiconductor controller chip which is electrically connected with another inner connecting terminals formed on the wiring board via the interposer chip.