Vertically Stacked Semiconductor Patterns for Carrier Mobility
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Solution Overview
Problem
Semiconductor devices face challenges in achieving higher reliability, speed, and multifunctionality due to limitations in carrier mobility and integration complexity.
Innovation Solution
A semiconductor device with a field effect transistor design that includes vertically stacked semiconductor patterns with different conductivities, a blocking layer, and specific manufacturing processes to enhance electrical characteristics, such as carrier mobility, by forming active patterns, barrier dielectric patterns, and gate structures on a substrate with distinct regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertically stacked semiconductor patterns with different conductivities are formed, then carrier mobility is enhanced, but device complexity increases
Solution Approach 1:
The patent transitions from planar semiconductor structures to vertically stacked three-dimensional structures. Multiple semiconductor patterns are stacked in the vertical direction (third direction) to form channel regions, allowing carriers to move through multiple channels simultaneously. This dimensional change increases carrier mobility without requiring larger lateral area, and the stacked configuration enables independent conductivity control of each layer to optimize device performance.
Solution Approach 2:
The semiconductor active region is divided into multiple discrete semiconductor patterns stacked vertically, with each pattern having distinct conductivity characteristics. These segmented patterns are spaced apart to form individual channel regions that can be independently controlled by gate structures. The segmentation allows different portions of the active region to have optimized conductivity for specific functions (e.g., drive current, threshold voltage control), thereby enhancing overall device performance while managing complexity through modular design.
2Reliability
If blocking layer is formed on recessed region of device isolation layer, then electrical characteristics are enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The blocking layer is formed in advance on the recessed region of the device isolation layer before subsequent processing steps. This preliminary placement ensures that the blocking layer is positioned correctly relative to the vertically stacked semiconductor patterns and gate structures. By preparing the blocking layer early in the manufacturing sequence, the patent ensures proper electrical isolation and contact characteristics are established before additional layers are deposited, reducing the need for high-precision alignment in later steps.
Solution Approach 2:
The blocking layer serves as an intermediary element between the device isolation layer and the vertically stacked semiconductor patterns. It provides electrical isolation in the recessed region while allowing controlled contact in other areas, mediating the electrical characteristics between different device regions. This intermediary structure simplifies the manufacturing process by providing a stable reference plane for subsequent layer deposition and reducing the precision requirements for aligning upper layers with underlying structures.
Data Source
AI summary
Disclosed are semiconductor devices including a field effect transistor and methods of manufacturing the same. The semiconductor device comprises a device isolation layer in an upper portion of a substrate, first active patterns on a first region of the substrate and second active patterns on a second region of the substrate, gate structures extending in one direction and running across the first and second active patterns, and a blocking layer on a recessed region of the device isolation layer of the first region. Each of the first and second active patterns comprises a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other. The semiconductor patterns of the first active patterns have conductivity different from that of the semiconductor patterns of the second active patterns. The blocking layer is limited on the first region.