3D Stacked Semiconductor Structure for Dense Multi-Core Interconnects
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Solution Overview
Problem
Current semiconductor structures face challenges in achieving greater computation capability within a smaller area and efficient data sharing/data switching due to complex connections between multiple cores, which require larger circuit areas.
Innovation Solution
A semiconductor structure with a front-to-front die-stacking design that includes a substrate, through vias, trench capacitors, redistribution layers, and bonded chips, allowing for efficient electrical connections and reduced thickness, enabling increased computation capability and faster data sharing/data switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple cores are used to improve computation capability, then computation capability is improved, but circuit area increases
Solution Approach 1:
The patent transitions from a planar arrangement of multiple cores to a three-dimensional stacked architecture. Multiple core dies are vertically stacked and bonded together, allowing computation capability to scale with the number of stacked layers rather than requiring proportional increases in lateral circuit area. This vertical stacking enables higher computation density by utilizing the third dimension (height) instead of only the two-dimensional plane.
Solution Approach 2:
The computing system is divided into multiple independent core dies that can be manufactured separately and then stacked. Each core die functions as an independent computational unit, and the segmentation allows for modular scaling of computation capability. The separate fabrication of individual core dies also enables specialized optimization for different computational tasks while maintaining a compact overall structure.
2Adaptability or versatility
If connections between cores are added to enable data sharing and switching, then data sharing capability is improved, but circuit area and complexity increase
Solution Approach 1:
The patent introduces intermediate structures including redistribution layers (RDLs), through-silicon vias (TSVs), and buffer dies that serve as mediators for data transmission between stacked core dies. These intermediary elements provide standardized interfaces and routing paths, simplifying the complexity of direct point-to-point connections between all cores. The buffer dies and RDLs act as intermediary stages that manage data flow and signal distribution across multiple layers.
Solution Approach 2:
Data connections transition from lateral routing within a single plane to vertical routing through stacked layers. Through-silicon vias provide direct vertical pathways for data transmission between cores on different layers, significantly reducing connection length and complexity compared to lateral routing. This vertical interconnection approach simplifies the routing topology by exploiting the third dimension for signal transmission.
3Productivity
If substrate thickness is reduced to accommodate stacking, then vertical integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The substrate thickness is pre-adjusted to a reduced value before the stacking process begins. This preliminary thinning of the substrate ensures that when multiple core dies are stacked, the overall package height remains within acceptable limits. By performing the thickness reduction in advance, the manufacturing process can better control and manage the cumulative tolerances across multiple stacking operations.
Solution Approach 2:
The substrate thickness parameter is changed from a standard value to a reduced value optimized for multi-die stacking. This parameter change enables better vertical integration by creating sufficient clearance between stacked cores while maintaining structural integrity. The modified thickness parameter also facilitates improved thermal management and signal integrity in the stacked configuration.
Data Source
AI summary
A semiconductor structure includes a substrate, a through via penetrating the substrate, a trench capacitor, a first RDL, a second RDL, a contact feature, and a chip. The trench capacitor extends from a back surface toward a front surface of the substrate, wherein the trench capacitor is separated from an active area at the front surface of the substrate. The first RDL is disposed over the front surface and electrically connecting to the through via. The second RDL is disposed over the back surface of the substrate and electrically connecting to the through via and the trench capacitor. The contact feature is disposed over the second RDL and electrically connecting to the trench capacitor through the second RDL. The chip is bonded over the front surface of the substrate. A method of manufacturing the semiconductor structure is also provided.