3D Stacked Semiconductor Package for Shorter Optical Signal Paths
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Solution Overview
Problem
The increased power consumption in co-packaged optics due to the relatively long signal connection path between the central processing unit and the optical engine in semiconductor packages.
Innovation Solution
A semiconductor package design that includes an interposer with specific layer configurations and through vias to minimize the optical signal transmission path, utilizing a photonic IC chip and electronic IC chip with overlapping physical layers to reduce signal distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If co-packaged optics is used with optical engine and semiconductor chips in one package, then integration is improved, but signal connection path becomes longer and power consumption increases
Solution Approach 1:
The patent transitions from a planar 2D arrangement of chips to a 3D stacked configuration where the photonic IC chip is positioned directly above the electronic IC chip. This vertical stacking in the third dimension dramatically shortens the signal connection path between the optical engine and central processing unit, thereby reducing power consumption while maintaining the integrated package structure.
2Device complexity
If signal connection path is lengthened for co-packaged optics layout, then package structure is simplified, but power consumption increases
Solution Approach 1:
By stacking the photonic IC chip vertically above the electronic IC chip, the patent utilizes the third dimension to minimize the signal transmission distance. This 3D arrangement maintains a relatively simple package structure while effectively reducing the power consumption associated with long signal paths.
3Ease of manufacture
If photonic IC chip and electronic IC chip are positioned far apart, then manufacturing is easier, but signal transmission distance increases and power consumption increases
Solution Approach 1:
The patent positions the photonic IC chip and electronic IC chip in direct vertical contact in the third dimension, minimizing the distance between them. This stacked configuration reduces signal transmission distance and power consumption while remaining compatible with standard semiconductor manufacturing processes for multi-chip packages.
Data Source
AI summary
A semiconductor package includes an interposer that includes a plurality of lower pads and a plurality of upper pads, a first semiconductor chip on the interposer, where the first semiconductor chip includes a first side portion and a second side portion, where the first semiconductor chip includes a first physical layer in a first region that is adjacent to the first side portion and a second physical layer in a second region that is adjacent to the second side portion, a photonic integrated circuit (IC) chip including a plurality of first through vias that at least partially overlap the second region, and an electronic IC chip on the photonic IC chip, where the electronic IC chip includes a third physical layer that at least partially overlaps the second region.