3D Stacked Semiconductor Structure With Oxide-Silicon Interconnects
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Solution Overview
Problem
Existing semiconductor devices face challenges in miniaturization, density, electrical performance, speed, power consumption, and reliability, particularly when using oxide semiconductors for transistors.
Innovation Solution
A semiconductor device structure comprising multiple layers with specific configurations, including single crystal and oxide semiconductor channels, conductive and insulating films, and conductive connections, optimized for miniaturization and high-density integration, with a novel stacked-layer oxide semiconductor structure and conductive connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If oxide semiconductors are used for transistors, then miniaturization and high-density integration are enabled, but electrical performance and reliability deteriorate
Solution Approach 1:
The patent transitions from planar transistor structures to vertically stacked three-dimensional transistor structures. Multiple transistor layers are stacked in the vertical dimension, enabling high-density integration while maintaining electrical performance through optimized vertical channel formation and gate control in the stacked configuration
Solution Approach 2:
The patent employs composite material structures including stacked layers of oxide semiconductors, nitride semiconductors, and other semiconductor materials with different properties. This composite approach allows optimization of electrical characteristics in each layer while achieving overall high-density integration and reliable operation
2Quantity of substance
If transistor miniaturization is pursued, then density increases, but manufacturing precision requirements worsen
Solution Approach 1:
The patent divides the semiconductor device into multiple discrete transistor layers stacked vertically. Each layer can be fabricated and processed separately with standardized procedures, then assembled into the final stacked structure. This segmentation enables high transistor density while maintaining manageable manufacturing precision requirements for each individual layer
Solution Approach 2:
The patent implements nested transistor structures where smaller transistors are integrated within larger transistor packages, and multiple transistor layers are nested vertically. This nesting approach maximizes transistor density within the available device volume while using modular fabrication units that maintain reasonable precision requirements
Data Source
AI summary
The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.