Stacked Semiconductor Package Adhesive Layer Design
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Solution Overview
Problem
Current semiconductor package designs face challenges in maximizing the number of integrated packages on a printed circuit board while minimizing space, particularly in stacked die configurations, due to difficulties in controlling the thickness of insulative films and stresses caused by thermal expansion coefficient differences, as well as manufacturing complexities in aligning and encapsulating larger top dies over smaller bottom dies.
Innovation Solution
A semiconductor package design featuring a substrate with a conductive pattern and insulative layer, where two or more semiconductor dies are electrically connected through conductive wires, with an adhesive or insulating layer that encapsulates the wires, and a package body that covers the dies and wires, allowing for precise alignment and encapsulation of larger top dies over smaller bottom dies without the need for separate insulative films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate insulative films are used between stacked semiconductor dies, then electrical insulation is achieved, but manufacturing complexity increases and thickness control becomes difficult
Solution Approach 1:
The patent combines the insulative layer and adhesive layer into a single integrated structure. The insulative layer is formed as part of the same film structure that provides adhesion between stacked semiconductor dies, eliminating the need for separate insulative films. This merging reduces manufacturing steps, simplifies thickness control, and maintains effective electrical insulation between dies.
2Adaptability or versatility
If larger top dies are stacked over smaller bottom dies, then package functionality is enhanced, but alignment and encapsulation difficulties arise
Solution Approach 1:
The patent extends the insulative layer laterally beyond the boundaries of the smaller bottom die to provide an oversized platform that accommodates the larger top die. This dimensional extension in the lateral direction facilitates easier alignment during stacking and provides sufficient adhesive surface area for secure bonding, resolving the encapsulation difficulties associated with mismatched die sizes.
3Adaptability or versatility
If more semiconductor packages are integrated on a printed circuit board, then device functionality increases, but space requirements conflict with miniaturization goals
Solution Approach 1:
The patent transitions from a planar arrangement of semiconductor packages to a three-dimensional stacked configuration. By stacking multiple semiconductor dies vertically on top of each other, the design utilizes the vertical dimension to increase package functionality and integrate more devices, thereby reducing the horizontal footprint required on the printed circuit board.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances manufacturing efficiency and reduces production costs by eliminating the need for separate insulative films, while maintaining effective electrical insulation and preventing current leakage, thus maximizing package density on a printed circuit board.
Implementation Method 1
an adhesive layer that bonds the first semiconductor die and the second semiconductor die to each other and to the substrate
Implementation Method 2
conductive wires, some of which may be fully or partially encapsulated by the adhesive layer, electrically connect the first semiconductor die and the second semiconductor die to the substrate
Data Source
AI summary
In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including two or more semiconductor dies which are electrically connected to an underlying substrate through the use of conductive wires, some of which may be fully or partially encapsulated by an adhesive or insulating layer of the package. In a basic embodiment of the present invention, the semiconductor package comprises a substrate having a conductive pattern disposed thereon. Electrically connected to the conductive pattern of the substrate are first and second semiconductor dies. The first semiconductor die and a portion of the substrate are covered by an adhesive layer. The second semiconductor die, the adhesive layer and a portion of the substrate are in turn covered by a package body of the semiconductor package.