Stacked Semiconductor Package Integrating Output Inductor
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Solution Overview
Problem
Conventional semiconductor packages with thinner power transistors still occupy an undesirably large area on circuit boards due to the external or side-by-side placement of output inductors, which is inefficient as devices trend towards smaller form factors.
Innovation Solution
A semiconductor package with a stacked architecture that integrates the output inductor, using a conductive carrier with a partially etched component side to reduce height and area requirements, allowing the power stage and integrated output inductor to be fabricated in a compact form without increasing the circuit board area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the output inductor is placed externally or side-by-side with the power transistors, then the package can accommodate all components, but the semiconductor package occupies an undesirably large area on the circuit board
Solution Approach 1:
The patent transitions from a planar side-by-side layout to a three-dimensional stacked architecture. The output inductor is positioned vertically above the power transistors on the same substrate, utilizing the vertical dimension to reduce the horizontal footprint on the circuit board while maintaining all necessary electrical connections through vertical vias and conductive structures.
Solution Approach 2:
The patent implements a nested configuration where the output inductor structure is integrated within the same package envelope as the power transistors. The inductor windings are positioned above the transistor active areas, with shared substrate real estate and overlapping footprints, effectively nesting one component within the spatial envelope of another to minimize overall package area.
2Reliability
If a conductive clip with large cross-sectional area is used for the switch node connection, then a reliable low resistance connection is achieved, but the package height increases
Solution Approach 1:
The patent divides the switch node connection into multiple segmented conductive paths rather than relying on a single large clip. The connection is distributed through multiple vias, trace segments, and conductive structures that collectively provide the necessary current carrying capacity and mechanical strength, reducing the need for a single large-height clip structure.
Solution Approach 2:
The patent transitions from a vertical clip structure extending upward to a distributed planar network of conductive traces and vias. The switch node connection is achieved through a two-dimensional network of conductive paths on the substrate and intermediate layers, eliminating the need for a tall vertical clip while maintaining electrical performance.
Data Source
AI summary
In one implementation, a power semiconductor package includes a conductive carrier including a switch node segment and a power output segment. The power semiconductor package also includes an integrated output inductor stacked over the conductive carrier and configured to couple the switch node segment to the power output segment. The power semiconductor package further includes a power stage stacked over the integrated output inductor, the power stage including a pulse-width modulation (PWM) control and driver coupled to a control transistor and a sync transistor.