Stacked Semiconductor Package Structure Without Intermediate PCB
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Solution Overview
Problem
Current semiconductor package structures face limitations in achieving high integration due to the presence of printed circuit boards, which restrict thickness reduction and increase process failure rates, hindering multi-functionalization.
Innovation Solution
A semiconductor package structure is designed without a printed circuit board between adjacent chip stacked structures, allowing for higher integration by sequentially stacking semiconductor chips and using solder balls and pads for electrical connections, while maintaining two printed circuit boards between middle and upper chip stacked structures for additional support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a printed circuit board is disposed between the lower chip stacked structure and the upper chip stacked structure, then the structural stability is improved, but the thickness reduction is limited
Solution Approach 1:
The patent removes the printed circuit board from between the lower and upper chip stacked structures, extracting the unnecessary component that was preventing thickness reduction. The electrical connections are reconfigured to eliminate the need for the intermediate printed circuit board, thereby achieving thickness reduction while maintaining structural integrity through alternative support mechanisms.
2Productivity
If the stacked number of semiconductor chips is increased in the lower chip stacked structure, then the integration is improved, but the process failure rate increases
Solution Approach 1:
The patent divides the chip stacked structure into separate lower and upper modules, each with a manageable number of stacked chips. This segmentation allows for better process control and reduced failure rates in each module while achieving high overall integration when the modules are combined. The lower chip stacked structure can be optimized independently from the upper structure.
3Ease of manufacture
If a printed circuit board is disposed between the lower chip stacked structure and the upper chip stacked structure, then the electrical connection is facilitated, but the multi-functionalization is hindered
Solution Approach 1:
The patent designs the chip stacked structures to perform multiple functions including electrical connection, mechanical support, and signal transmission without requiring a separate printed circuit board. The semiconductor chips themselves are configured to provide these multiple functions, enabling multi-functionalization while maintaining ease of electrical connection through direct pad-to-pad or pad-to-solder ball connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the overall thickness of the semiconductor package, decreases process failure rates, and enhances multi-functionalization capabilities by eliminating the need for printed circuit boards between chip stacks, thereby increasing the degree of freedom in chip arrangement and functionality.
Implementation Method 1
at least one first solder ball disposed on the second package and at least one second solder ball disposed on the fourth package. The at least one first pad and the at least one second pad are in contact with the at least one first solder ball, and the at least one third pad and the at least one fourth pad are in contact with the at least one second solder ball.
Implementation Method 2
The at least one second pad is electrically connected to the at least one second semiconductor chip. The at least one fourth pad is electrically connected to the at least one fourth semiconductor chip
Data Source
AI summary
The semiconductor package structure includes first and second packages. The first package has at least one first semiconductor chip disposed on a first printed circuit board, and at least one first pad disposed on the at least one first semiconductor chip. The second package has at least one second pad disposed on the first package, and at least one second semiconductor chip disposed on the at least one second pad. The at least one first semiconductor chip is electrically connected to the first printed circuit board. The at least one second pad is electrically connected to the at least one second semiconductor chip. The at least one second pad faces the at least one first pad.