Stacked Semiconductor Package with Plated Mold Layer
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Solution Overview
Problem
The challenge lies in creating a semiconductor package that can be miniaturized and integrated in a high-density form while maintaining a lightweight and slim profile, which is essential for modern wireless communication terminals and cellular phones, where traditional technologies for reducing part sizes and integrating multiple devices into one package are insufficient.
Innovation Solution
A semiconductor package is developed comprising a chip part mounted on a board, protected by a mold member, with a plated layer featuring an electrode pattern that connects to the board's wiring pattern, allowing for the stacking of additional semiconductor packages and efficient electrical connections, enabling the creation of an ultra-miniature package assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If traditional packaging technologies are used, then device functionality is maintained, but device size and weight cannot be sufficiently reduced
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked packaging, where multiple semiconductor packages are vertically stacked and connected through plated holes in mold members. This dimensional change enables significant reduction in footprint area while maintaining connection reliability through direct vertical interconnections.
Solution Approach 2:
The patent implements a nested structure where smaller semiconductor packages are mounted on larger ones, and mold members encapsulate multiple chip parts. The plated holes penetrate through mold members to establish connections between stacked packages, creating a nested configuration that maximizes space utilization and reduces overall package size.
2Area of stationary object
If multiple devices are integrated into one package, then space efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the integrated package into modular semiconductor packages, each containing a chip part and mold member. These standardized modules can be independently manufactured and then stacked, simplifying the overall manufacturing process despite the complex three-dimensional integration. Each module maintains relatively simple internal structure while achieving complex system-level integration.
3Volume of moving object
If package size is reduced, then miniaturization is achieved, but electrical connection reliability may deteriorate
Solution Approach 1:
The patent incorporates plated holes and electrode patterns during the mold member formation process, before the actual stacking and assembly operations. This preliminary preparation of connection structures ensures precise alignment and reliable electrical connections between stacked packages, maintaining manufacturing precision even as package volume is reduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for the realization of an ultra-miniature package assembly, enabling efficient space utilization and high-density integration, thereby securing space within compact devices like cellular phones and headsets.
Implementation Method 1
a plated layer comprising an electrode pattern connected to a pattern of the board on the mold member
Data Source
AI summary
Provided are a semiconductor package and a manufacturing method thereof. A semiconductor package according to an embodiment comprises a chip part on a board, a mold member, and a plated layer on the mold member. The plated layer comprises an electrode pattern connected to a pattern of the board. The electrode pattern of the plated layer can be mounted at least one of at least one a chip part and at least one another semiconductor package.