Stacked Semiconductor Package with Thick Wafer Support

Solution Overview

Problem

Current semiconductor technologies face challenges in achieving high integration and multifunctionality due to limitations in stacking semiconductor chips vertically, leading to mechanical damage and defects during processing, especially when forming memory chip stacks over thin logic wafers.

Innovation Solution

A semiconductor package is fabricated by stacking multiple first semiconductor chips vertically over a thick semiconductor wafer, with a second semiconductor chip acting as a logic chip, and a molding layer surrounding the stack to mitigate mechanical damage and facilitate high integration and multifunctionality, while also allowing for a desired thin thickness through wafer thinning.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple semiconductor chips are stacked vertically to achieve high integration, then the degree of integration is improved, but mechanical damage and defects occur during processing

Engineering Contradiction:

Improvedegree of integrationVSAvoidmechanical damage and defects

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

A thick semiconductor wafer is prepared in advance before stacking the memory chip stacks. This preliminary preparation of a robust substrate provides mechanical support during subsequent processing steps, preventing warpage and cracking that would occur with thin wafers.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The thick semiconductor wafer acts as a cushioning layer that absorbs mechanical stress during dicing and other processing operations. This cushioning effect protects the stacked memory chips from damage while enabling high integration.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Length of stationary object

If a thin wafer is used to reduce package thickness, then the package size is reduced, but cracking and warpage occur during processing

Engineering Contradiction:

Improvepackage thicknessVSAvoidresistance to cracking and warpage

Core Design Contradiction:

Length of stationary objectVSStrength

Solution Approach 1:

A thick semiconductor wafer is prepared in advance before stacking the memory chip stacks. This preliminary preparation of a robust substrate provides mechanical support during subsequent processing steps, preventing warpage and cracking that would occur with thin wafers.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The solution transitions from using a thin wafer (single dimension optimization) to using a thick wafer (different dimensional approach). By changing the wafer thickness dimension, the patent achieves both mechanical strength during processing and enables subsequent thinning to achieve thin final package dimensions.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 3:

The wafer thickness parameter is changed from thin to thick during the stacking process to provide mechanical strength, and then subsequently thinned after stacking is complete. This parameter change enables both processing reliability and final package thinness.

Inventive Principle:

Principle #35Parameter changes

3Strength

If a thick semiconductor wafer is used to prevent mechanical damage, then structural strength is improved, but the final package thickness increases

Engineering Contradiction:

Improveresistance to mechanical damageVSAvoidpackage thickness

Core Design Contradiction:

StrengthVSLength of stationary object

Solution Approach 1:

A thick semiconductor wafer is prepared in advance before stacking the memory chip stacks. This preliminary preparation of a robust substrate provides mechanical support during subsequent processing steps, preventing warpage and cracking.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The wafer thickness parameter is changed from thin to thick during the stacking process to provide mechanical strength, and then subsequently thinned after stacking is complete. This parameter change enables both processing reliability and final package thinness.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11569216B2Semiconductor package including stacked semiconductor chips and method for fabricating the semiconductor package

Publication Date: 2023.01.31 SK HYNIX INC

AI summary

A semiconductor package includes: a second semiconductor chip including a second through electrode that penetrates a second body portion and a second connection electrode that is connected to one end of the second through electrode; a first semiconductor chip stack disposed over the second semiconductor chip and including a plurality of first semiconductor chips, each of the plurality of first semiconductor chips includes a first through electrode and a first connection electrode connected to one end of the first through electrode; a molding layer; a third semiconductor chip disposed over the molding layer and the first semiconductor chip stack; and an external connection electrode electrically connected to an other end of the second through electrode, wherein, the second semiconductor chip and the plurality of first semiconductor chips are electrically connected through the second through electrode, the second connection electrode, the first through electrodes, and the first connection electrodes.