Stacked Semiconductor Package Through Electrode Alignment
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Solution Overview
Problem
The challenge in semiconductor packaging is the misalignment of through electrodes in stacked semiconductor packages, which leads to gaps between chips, increasing the package volume and causing process defects.
Innovation Solution
The solution involves forming through electrodes that pass through semiconductor chips with recessed areas on one face, where a connection member, such as solder or an anisotropic conductive resin with conductive balls, is placed to electrically connect adjacent chips, ensuring direct contact and preventing misalignment during stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through electrodes are used to connect stacked semiconductor chips, then electrical connectivity between chips is achieved, but misalignment of through electrodes occurs leading to gaps between chips
Solution Approach 1:
The patent applies preliminary action by forming a protrusion on the through electrode before stacking the chips. This protrusion预先 extends beyond the chip surface, allowing it to make contact with the corresponding recess in the upper chip during the stacking process. This preliminary structural preparation ensures proper alignment and eliminates gaps between stacked chips, resolving the misalignment issue while maintaining electrical connectivity.
2Ease of manufacture
If gaps are present between stacked semiconductor chips, then misalignment is tolerated, but package volume increases
Solution Approach 1:
The protrusion structure is formed in advance on the through electrode, extending beyond the chip surface before stacking. This preliminary action ensures that when chips are stacked, the protrusion fills any potential gaps and makes direct contact with the upper chip's recess, eliminating voids and reducing overall package volume while maintaining manufacturing feasibility.
Solution Approach 2:
The protrusion of the lower chip's through electrode nests into the recess of the upper chip, creating an interlocking structure. This nesting arrangement eliminates gaps between chips and reduces package volume, while the complementary geometric shapes ensure proper alignment during stacking.
3Reliability
If through electrodes extend through the entire chip thickness, then electrical connection is established, but misalignment causes gaps and process defects
Solution Approach 1:
The patent applies local quality by creating a protrusion at a specific location on the through electrode (extending beyond the chip surface) while the rest of the electrode remains within the chip. This localized structural modification ensures reliable electrical connection through the protrusion contact with the upper chip, while preventing process defects by eliminating gaps that would otherwise form due to misalignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates gaps between semiconductor chips, reduces package volume, and prevents process defects by ensuring precise alignment and electrical connectivity between stacked chips.
Implementation Method 1
A connection member is disposed in the recess part to electrically connect the through electrodes of adjacent stacked semiconductor chips
Data Source
AI summary
A stacked semiconductor package includes a semiconductor chip module including at least two semiconductor chips, each semiconductor chip having a first face, a second face opposite to the first face, and a circuit part. A through portion passes through the first and second faces of the semiconductor chip. A recess part is formed in a portion of the second face where the second face and the through portion meet. A through electrode is electrically connected to the circuit part and is disposed inside of the through portion. A connection member is disposed in the recess part to electrically connect the through electrodes of adjacent stacked semiconductor chips. And the semiconductor chip module is mounted to a substrate. The stacked semiconductor package prevents both gaps between semiconductor chips and misalignment of the through electrode.