Stacked Semiconductor Package with Through Structures for Heat Dissipation
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving improved thermal characteristics and reliability, particularly in compact designs where heat management and electrical connectivity are critical for efficient operation.
Innovation Solution
A semiconductor package configuration is proposed, featuring stacked chips with specific through structures and conductive vias that allow for direct electrical connections and efficient heat dissipation, including a logic chip on top for enhanced thermal management and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If chips are stacked vertically to reduce package size, then compactness is improved, but heat dissipation becomes more difficult
Solution Approach 1:
The patent transitions from horizontal heat dissipation in traditional lateral packaging to vertical heat dissipation through the stacked chip structure. Heat sinks and thermal management components are positioned at the top and bottom surfaces of the stack, utilizing the vertical dimension to conduct heat away from the densely packed chips, thereby solving the heat dissipation challenge in compact packages.
Solution Approach 2:
The package is segmented into multiple functional layers with dedicated thermal management zones. Different chips in the stack can have different thermal characteristics, and the structure allows for separate thermal pathways through top and bottom heat sinks, enabling independent thermal control for different functional blocks within the compact volume.
2Reliability
If through structures are used to penetrate semiconductor substrates for electrical connection, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
Through structures are formed in the semiconductor substrates before chip stacking, allowing alignment and connection to be established in advance. This preliminary formation of through-holes or through-silicon vias enables subsequent bonding processes to be simpler and more reliable, as the electrical pathways are pre-configured rather than requiring complex post-assembly routing.
Solution Approach 2:
The through structures act as intermediary elements that bridge multiple chip layers. These conductive pathways penetrate the substrate and provide direct electrical connection between upper and lower chips, eliminating the need for complex wire bonding or trace routing through intermediate connection layers, thereby improving reliability while managing manufacturing complexity.
3Adaptability or versatility
If multiple dummy chips are stacked to achieve electrical connection routing, then device functionality is improved, but package volume increases
Solution Approach 1:
The dummy chips are designed with multi-functionality, serving both as electrical connection intermediaries and as part of the overall package structure. Their substrates and conductive vias are configured to provide routing pathways while their physical presence contributes to the structural integrity and thermal management of the package, thereby achieving routing functionality without proportional volume increase.
Solution Approach 2:
The electrical connection pathways are nested within the dummy chip structures rather than requiring separate external routing layers. The conductive vias and traces are integrated into the dummy chip substrate thickness, allowing connection routing to be embedded within the existing package volume rather than adding external expansion.
Data Source
AI summary
Disclosed is a semiconductor package comprising a first memory chip including a first semiconductor substrate and a first through structure that penetrates the first semiconductor substrate, a second memory chip that directly contacts a top surface of the first memory chip and includes a second semiconductor substrate and a second through structure that penetrates the second semiconductor substrate, a first dummy chip that directly contacts a top surface of the second memory chip and includes a first conductive via, a second dummy chip that directly contacts a top surface of the first dummy chip and includes a second conductive via, and a logic chip in direct contact with a top surface of the second dummy chip. The logic chip is electrically connected to the first through structure through the second conductive via, the first conductive via, and the second through structure.