3D Stacked Semiconductor Package with TMVs and TSVs
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Solution Overview
Problem
The complexity of manufacturing semiconductor devices increases due to the combination of various materials with different thermal properties, necessitating improved manufacturing processes and packaging solutions for miniaturized, high-functionality semiconductor packages.
Innovation Solution
A semiconductor package structure and method involving a first die, a second die, a redistribution layer (RDL), molding, and conductive members, where the first die is electrically connected to the RDL through through-molding vias (TMVs) and the second die is connected through through-silicon vias (TSVs), simplifying electrical connections and reducing package size through vertical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a stack of at least two chips (or dies) in a 3D package is used to form a memory device, then memory capacity is doubled and mounting density is improved, but manufacturing complexity increases due to combination of various materials with different thermal properties
Solution Approach 1:
The patent transitions from planar (2D) packaging to three-dimensional (3D) stacked packaging, arranging multiple dies vertically in the Z-dimension. This dimensional change enables doubled memory capacity and improved mounting density while managing manufacturing complexity through systematic process design
2Device complexity
If through-molding vias (TMVs) and through-silicon vias (TSVs) are used for electrical connections, then electrical connection simplicity is improved and package size is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent merges multiple electrical connection functions into unified via structures. TMVs and TSVs serve dual purposes: providing electrical interconnects between dies and serving as alignment/registration features during bonding, thereby simplifying the overall electrical connection architecture while managing manufacturing complexity
3Adaptability or versatility
If various materials with different thermal properties are combined in semiconductor assembly, then functionality and integration are improved, but manufacturing operation complexity increases
Solution Approach 1:
The patent applies local quality by selecting specific materials with appropriate thermal properties for specific locations and functions within the stacked package. Different die substrates, molding compounds, and interconnect materials are chosen based on their local thermal management requirements, enabling high integration while managing manufacturing complexity through material optimization
Data Source
AI summary
The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a first die, at least a second die, an RDL disposed over the second die, a molding encapsulating the first die and the second die, a plurality of first conductors disposed in the molding, and a plurality of second conductors disposed in the second die. The first die has a first side and a second side opposite to the first side. The second die has a third side facing the first side of the first die and a fourth side opposite to the third side. The RDL is disposed on the fourth side of the second die. The first die is electrically connected to the RDL through the plurality of first conductors, and the second die is electrically connected to the RDL through the plurality of second conductors.