3D Stacked Semiconductor Package with Vertical Interconnectors
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Solution Overview
Problem
The challenge is to create a semiconductor package that efficiently integrates multiple semiconductor chips while maintaining reliability, particularly in terms of heat dissipation performance, to meet the demand for miniaturized and lightweight electronic components in portable devices.
Innovation Solution
A semiconductor package is designed with a base substrate, lower and upper semiconductor chips, an intermediate connection member with redistribution layers, and vertical interconnectors, along with a molding portion that surrounds the chips and interconnectors, allowing for efficient heat dissipation and secure coupling of the chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips are integrated in a stack structure to reduce size and weight, then miniaturization and weight reduction are achieved, but heat dissipation performance deteriorates
Solution Approach 1:
The patent transitions from planar chip arrangement to a three-dimensional stack structure, stacking semiconductor chips vertically on the base substrate. This dimensional change allows efficient use of limited package area while incorporating thermal management components in the vertical dimension, such as heat dissipation structures beneath the substrate and side surfaces, thereby addressing heat dissipation challenges in miniaturized packages.
Solution Approach 2:
The patent introduces a base substrate as an intermediary component between the semiconductor chips and the heat dissipation structures. The substrate serves as a thermal pathway, conducting heat away from the stacked chips through its thickness and distributing it to heat dissipation structures on the opposite surface, thus mediating the thermal management in the compact stack configuration.
2Productivity
If multiple semiconductor chips are stacked to achieve high integration, then chip density increases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the semiconductor package into distinct functional modules: a base substrate, multiple semiconductor chips stacked in sequence, intermediate connection members between chips, and peripheral heat dissipation structures. This segmentation allows each component to be manufactured and prepared separately using standard processes, then assembled into the final stack configuration, reducing overall manufacturing complexity while achieving high integration density.
Solution Approach 2:
The patent implements a nested structure where semiconductor chips are stacked one on top of another, with intermediate connection members nested between the chips. The base substrate serves as the outer container supporting the entire stack, while heat dissipation structures are positioned on the opposite side of the substrate, creating a compact nested arrangement that maximizes space utilization and simplifies assembly.
3Reliability
If vertical interconnectors are disposed around the lower semiconductor chip to connect redistribution layers, then electrical connectivity is improved, but package area is consumed
Solution Approach 1:
The patent utilizes the vertical dimension by extending interconnectors upward from the base substrate to connect with the active surfaces of stacked semiconductor chips. This vertical interconnection approach eliminates the need for extensive lateral routing on the substrate plane, thereby maintaining electrical connectivity reliability while preserving valuable package area for active components and heat dissipation structures.
Solution Approach 2:
The patent concentrates interconnection resources at specific locations where chips are stacked and connected, rather than distributing complex routing across the entire substrate. The vertical interconnectors are strategically positioned at chip perimeters or corners, providing localized high-density connectivity where needed while leaving the rest of the substrate area available for other functions.
Data Source
AI summary
A semiconductor package includes: a base substrate including a lower redistribution layer; a lower semiconductor chip including a first active surface and on the base substrate; an upper semiconductor chip including a second active surface on the lower semiconductor chip and having an area larger than that of the lower semiconductor chip; an intermediate connection member including an upper redistribution layer on the second active surface of the upper semiconductor chip between the lower and upper semiconductor chips; a plurality of vertical interconnectors disposed around the lower semiconductor chip on the base substrate and connecting the lower redistribution layer and the upper redistribution layer; and a molding portion on the base substrate and including a first portion surrounding the lower semiconductor chip and the vertical interconnectors, and a second portion extending upwardly from the first portion and on side surfaces of the upper semiconductor chip and the intermediate connection member.