Stacked Semiconductor Packages with Vertical Molding Pattern
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Solution Overview
Problem
The development of highly integrated and high-speed semiconductor devices poses challenges in manufacturing due to increased complexity and demand for efficient electrical connections between stacked semiconductor packages, which existing technologies have not adequately addressed.
Innovation Solution
A semiconductor device comprising stacked semiconductor packages with a connecting pattern and a molding pattern that extends vertically to cover the sidewall of one package, using an exposure mold underfill (e-MUF) structure and underfill material to simplify manufacturing and enhance electrical connectivity, while dispersing stress across the packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If stacked semiconductor packages are used to achieve high integration, then device functionality and integration level are improved, but manufacturing complexity and difficulty of electrical connection increase
Solution Approach 1:
The invention divides the semiconductor device into multiple separate packages (first package, second package, third package) that are stacked vertically. Each package contains its own substrate, semiconductor chip, and mold part, allowing independent manufacturing and assembly. This segmentation enables complex functionality to be achieved through modular stacking rather than monolithic integration, resolving the contradiction between high integration and manufacturing complexity.
Solution Approach 2:
The invention transitions from planar integration to three-dimensional vertical stacking. By arranging multiple semiconductor packages in the vertical dimension (stacked configuration), the device achieves higher integration density without increasing planar footprint. This dimensional change allows multiple functional units to coexist in a compact space while maintaining separate manufacturing processes for each package.
2Adaptability or versatility
If electrical connections between stacked packages are established, then device functionality is improved, but manufacturing precision requirements increase
Solution Approach 1:
The invention introduces a connecting pattern as an intermediary element between the first and second packages. This connecting pattern includes conductive structures (such as solder balls, bumps, or trace patterns) that facilitate electrical connection between packages. The intermediary connecting pattern absorbs alignment tolerances and simplifies the bonding process, reducing the precision requirements compared to direct package-to-package connection.
Solution Approach 2:
The connecting patterns are prepared in advance on the substrates before final package assembly. The first substrate includes first connecting patterns and the second substrate includes second connecting patterns that are pre-formed and positioned. This preliminary preparation of connection interfaces allows for easier alignment and bonding during assembly, reducing the precision demands of the final assembly process.
3Strength
If mold parts cover semiconductor chips in stacked packages, then structural integrity is improved, but stress concentration between packages increases
Solution Approach 1:
The invention applies different local qualities to different regions of the package structure. The mold parts provide localized protection and structural support to individual semiconductor chips while allowing stress distribution throughout the overall stacked structure. The third package's mold part specifically covers the second package, creating a protective enclosure that distributes mechanical stress rather than concentrating it at single points.
Solution Approach 2:
The mold parts serve as protective enclosures that cushion and absorb mechanical stress before it can concentrate on the semiconductor chips. By providing this protective layer in advance, the structure prevents stress concentration that would otherwise occur at chip-package interfaces, thereby maintaining structural integrity while reducing stress on critical components.
4Stress or pressure
If underfill material is used in molding pattern, then stress dispersion is improved, but manufacturing process complexity increases
Solution Approach 1:
The invention utilizes the material properties of underfill (a type of molding material) to achieve stress dispersion. The underfill material has specific mechanical properties (flexibility, adhesive characteristics, stress distribution capabilities) that allow it to absorb and distribute mechanical stress throughout the package structure. By selecting and applying this specific material, the patent achieves stress dispersion without requiring complex additional structural elements.
Data Source
AI summary
A semiconductor device includes a first semiconductor package including a first mold part, a second semiconductor package including a second mold part, a connecting pattern configured to electrically connect the first and second semiconductor packages to each other, and a molding pattern between the first and second semiconductor packages. The molding pattern extends to cover at least a portion of a sidewall of only the second semiconductor package.