Stacked Semiconductor Packages Vertical Through Electrode Interconnect
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Solution Overview
Problem
Current semiconductor package technologies face challenges in reducing the area required for connecting upper and lower packages, which hinders the enhancement of structural and electrical characteristics in stacked semiconductor packages.
Innovation Solution
The implementation of a stacked semiconductor package design where upper and lower packages are electrically connected through a through electrode, with a first semiconductor package including a printed circuit board and a semiconductor device, and a second package stacked on top, featuring conductive patterns and molding structures to enhance connectivity and reduce the necessary connection area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional semiconductor package connection methods are used, then electrical connections between upper and lower packages can be established, but the area required for connecting packages is large
Solution Approach 1:
The patent transitions from horizontal planar connections to vertical three-dimensional connections by forming through electrodes that penetrate the lower package substrate and connect to the upper package vertically. This dimensional change allows electrical connections to be established in the vertical direction rather than requiring large horizontal connection areas, thereby reducing the overall package footprint while maintaining connection reliability
Solution Approach 2:
The patent introduces an interposer substrate as an intermediary component between the upper and lower packages. This interposer contains through electrodes that facilitate vertical electrical connections, acting as a mediator that enables compact three-dimensional stacking while ensuring reliable electrical connectivity between packages without requiring large connection areas
2Area of stationary object
If package size is reduced to improve compactness, then product compactness is enhanced, but the area for electrical connections becomes insufficient
Solution Approach 1:
The patent enables package size reduction by reforming electrical connections from horizontal to vertical orientation. Through electrodes penetrate the package substrates vertically, allowing connections to be made in the thickness direction rather than requiring extended planar areas. This dimensional reorientation permits compact package footprints while maintaining adequate electrical connection capability
Solution Approach 2:
The patent implements a nested three-dimensional package structure where the upper package is stacked vertically on top of the lower package, with both packages containing functional devices and interconnection structures. This nesting arrangement allows multiple packages to occupy a small horizontal footprint by utilizing the vertical dimension, thereby achieving compactness without compromising electrical connection ease through the through-electrode architecture
3Productivity
If vertical stacking is implemented to reduce horizontal mounting area, then integration density is enhanced, but structural complexity increases
Solution Approach 1:
The patent divides the semiconductor system into discrete, modular package units (lower package, interposer, upper package) that can be independently fabricated and then vertically stacked. Each segment contains its own substrate, semiconductor devices, and interconnection structures. This segmentation enables high integration density through vertical stacking while managing structural complexity by standardizing each modular unit with consistent through-electrode and interconnection architectures
Solution Approach 2:
The patent employs universal through-electrode structures and standardized interconnection interfaces that serve multiple functions: providing electrical connectivity, enabling mechanical support, and facilitating thermal management. This multi-functionality reduces the number of separate components needed, thereby enhancing integration density while preventing excessive increases in structural complexity through component consolidation
Data Source
AI summary
Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.