Stacked Semiconductor Packages With Through-Hole Wire Bonding
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Solution Overview
Problem
There is a limitation in improving the performance of semiconductor chips due to difficulties in developing the fabrication process, leading to challenges in increasing the number of semiconductor chips in a single semiconductor package, which affects data processing performance.
Innovation Solution
The semiconductor package design includes a package substrate with intersecting through holes and strategically positioned semiconductor chips, using bonding wires to electrically connect the chips, allowing for efficient stacking and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor chips are stacked on a package substrate to increase the number of chips, then the data processing performance is improved, but the fabrication process complexity increases
Solution Approach 1:
The patent transitions from a planar arrangement of semiconductor chips to a three-dimensional stacked configuration. Multiple chips are arranged vertically on the package substrate, utilizing the Z-dimension to increase integration density. This dimensional change allows more chips to be accommodated within the same footprint area, thereby improving data processing performance without proportionally increasing fabrication complexity
Solution Approach 2:
The patent implements a nested structure where semiconductor chips are stacked vertically on the package substrate, with each chip positioned above the previous one. The connection members (bonding wires or bumps) penetrate through the substrate to establish electrical connections between stacked chips, creating a nested arrangement similar to dolls within dolls. This nesting approach maximizes space utilization and enables high-density integration
2Productivity
If the number of semiconductor chips in a single package is increased, then the data processing performance is improved, but the package size increases
Solution Approach 1:
The patent resolves the package size issue by moving from a two-dimensional planar expansion to a three-dimensional vertical stacking approach. Instead of increasing the package footprint area to accommodate more chips, the design stacks chips vertically, utilizing the height dimension. This allows multiple chips to be integrated within a compact package volume, maintaining small package size while improving data processing performance through increased chip count
3Ease of manufacture
If bonding wires are used to electrically connect stacked semiconductor chips, then the ease of manufacture is improved, but the device complexity increases
Solution Approach 1:
The patent extracts the connection function from the chip-to-substrate interface and implements it through through-substrate vias that penetrate the package substrate. This separation allows bonding wires to be used exclusively for inter-chip connections in the vertical stack, while the substrate provides dedicated through-holes for electrical pathways. This extraction simplifies the overall connection structure by dividing responsibilities between the substrate and the bonding wires, making the manufacturing process more manageable despite the increased device complexity
Data Source
AI summary
A semiconductor package includes a package substrate having a hole pattern including a first through hole extending in a first direction and a second through hole extending in a second direction substantially perpendicular to the first direction, at least one first semiconductor chip disposed on the package substrate to overlap with the first through hole, at least one second semiconductor chip disposed on the package substrate to overlap with the second through hole, first bonding wires passing through the first through hole to electrically connect the at least one first semiconductor chip to the package substrate, and second bonding wires passing through the second through hole to electrically connect the at least one second semiconductor chip to the package substrate.