Stacked Semiconductor Pad Layout for Shorter RC Wiring Paths
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Solution Overview
Problem
Existing semiconductor apparatuses face challenges in improving the arrangement of connection pads and wiring characteristics between stacked semiconductor components, leading to suboptimal performance, size, and integration.
Innovation Solution
The semiconductor apparatus is designed with a specific arrangement of pads and wirings where overlapping pads form a triangular or cross configuration, allowing for efficient electrical connections and reduced wiring path lengths, thereby enhancing performance and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If connection pads are arranged in a conventional linear or grid pattern, then the wiring layout is simple, but the wiring path length increases and parasitic capacitance increases
Solution Approach 1:
The patent transitions from conventional linear or grid pad arrangements to a triangular arrangement where pads are positioned at vertices of triangles. This geometric transformation optimizes the spatial distribution of connection points, reducing the average distance between pads and cells while maintaining layout simplicity. The triangular configuration allows for more efficient routing paths compared to traditional arrangements.
2Length of stationary object
If connection pads are arranged to overlap with the cell array, then the wiring path length is reduced, but parasitic capacitance increases due to closer spacing
Solution Approach 1:
The patent applies different arrangement strategies to different regions of the pad array. By using triangular arrangements with varying orientations and spacing in different areas, the design optimizes the balance between wiring path length and parasitic capacitance locally. This allows regions with different requirements to have optimized pad configurations suited to their specific needs.
3Area of stationary object
If the semiconductor apparatus is downsized by overlapping components, then the integration density increases, but the wiring characteristics and yield rate deteriorate
Solution Approach 1:
The patent employs asymmetric triangular arrangements of connection pads rather than symmetric grid patterns. This asymmetry allows for optimized routing paths that avoid congestion and reduce crosstalk, improving wiring characteristics. The asymmetric layout provides better separation between signal paths while maintaining compact overall dimensions, thereby improving yield rate despite the downsized form factor.
Data Source
AI summary
A semiconductor apparatus according to the present invention includes: a semiconductor component including a cell array and a plurality of wirings; and a semiconductor component including a plurality of pads connected to the semiconductor component including the cell array. A first row pad connected to a row wiring connected to a first cell and a second cell, a second row pad connected to a row wiring connected to a third cell and a fourth cell, and a column pad connected to a column wiring connected to the first cell and the third cell are arranged such that a straight line connecting the first row pad and the column pad crosses a straight line connecting the second row pad and the column pad.