Stacked Semiconductor Package with Parallel Memory Access
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Solution Overview
Problem
Conventional stacked semiconductor packages face inefficiencies in data input/output operations due to serial chip selection signals, which slow down data access to specific memory devices, and existing stacking techniques do not adequately address the need for high-speed data transfer and reduced power consumption in portable consumer electronics.
Innovation Solution
A semiconductor package design featuring a logic device with a serializer/deserializer (SerDes) that connects odd and even memory devices in parallel, utilizing through-silicon vias and conductive bumps to facilitate fast data transfer between memory devices and the logic device, allowing simultaneous access and high-speed data input/output operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory devices are connected in series with the logic device, then device complexity is reduced, but data input/output speed decreases and power consumption increases
Solution Approach 1:
The memory devices are divided into two groups: odd memory devices connected to one set of signal lines and even memory devices connected to another set of signal lines. This segmentation allows parallel data access while managing connection complexity through organized signal routing.
Solution Approach 2:
The patent transitions from a single-dimension serial connection to a multi-dimensional parallel connection structure. Multiple memory devices are connected simultaneously through different signal line paths, enabling concurrent data operations and improving I/O speed without proportionally increasing complexity.
2Quantity of substance
If multiple memory devices are stacked on the logic device, then storage capacity increases, but data access time increases due to serial chip selection
Solution Approach 1:
Memory devices are segmented into odd and even groups with dedicated signal line connections. This allows the logic device to access multiple memory devices simultaneously through different signal paths, eliminating the need for sequential chip selection and reducing data access time while maintaining increased storage capacity.
Solution Approach 2:
The parallel connection structure enables continuous data operations across multiple memory devices without interruption. While one memory device is being accessed, other devices can simultaneously perform data operations, eliminating idle time and maintaining continuous useful action throughout the memory system.
3Productivity
If serial chip selection signals are used for memory access, then device complexity is reduced, but power consumption increases and data access speed decreases
Solution Approach 1:
The signal transmission paths are segmented into separate channels for odd and even memory devices. This allows simultaneous data operations on multiple devices without requiring sequential chip selection signals, improving data access efficiency while reducing power consumption by eliminating repeated signal transmission overhead.
Solution Approach 2:
Multiple memory devices are pre-configured with dedicated signal line connections during manufacturing. This preliminary action eliminates the need for dynamic chip selection signaling during operation, allowing immediate data access and reducing both power consumption and access time by avoiding repeated signal establishment.
Data Source
AI summary
A semiconductor package includes a base substrate, a logic device with a serializer/deserializer (SerDes), a plurality of odd memory devices disposed on a lower surface of the logic device and operatively stack-connected with the SerDes, and a plurality of even memory devices disposed on an upper surface of the logic device and operatively stack-connected with the SerDes, such that the plurality of odd memory devices and the plurality of even memory devices are connected in parallel by the SerDes.