Stacked Semiconductor Device with Integrated Peltier Element
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Solution Overview
Problem
In three-dimensional integrated circuit configurations, heat management is challenging, particularly when high power-consuming chips are stacked, as the efficient thermal coupling of the rear side of high power devices with external heat sinks is compromised, limiting overall heat dissipation capabilities and device performance.
Innovation Solution
Implementing a distributed Peltier element across stacked semiconductor devices, with one substrate acting as a heat sink and the other as a heat source, to create an active heat transfer system that efficiently transfers waste heat from high power devices to an external heat sink, maintaining thermal coupling similar to single device configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked in a three-dimensional configuration to increase volume density, then the volume packing density of circuit elements is improved, but the heat dissipation capability is worsened due to compromised thermal coupling of high power devices with external heat sinks
Solution Approach 1:
A Peltier element is introduced as an intermediary component between the high power-consuming chip and the low power-consuming chip. The Peltier element actively transfers heat from the high power chip through the low power chip to the external heat sink, resolving the thermal coupling problem created by the stacked configuration while preserving the volume density benefits.
Solution Approach 2:
The passive thermal conduction mechanism is replaced with an active thermoelectric cooling system using the Peltier element. This substitution enables controlled heat transfer across the stacked chips, overcoming the limitations of natural heat dissipation paths in three-dimensional configurations.
2Speed
If the number of circuit elements per unit area is increased to improve performance, then the switching speed and signal processing performance are improved, but the complexity of interconnect structures increases requiring more metallization layers
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional stacked configuration. By stacking multiple chips vertically, the interconnect complexity is distributed across multiple layers in the vertical dimension, allowing each individual chip to maintain simpler interconnect structures while achieving high overall system complexity and performance.
3Loss of time
If sophisticated low-k dielectric materials are used in metallization systems to reduce parasitic RC time constants, then signal propagation delay is reduced, but the mechanical stability of dielectric materials is worsened
Solution Approach 1:
The patent divides the single-chip system into multiple separate chips stacked in three dimensions. This segmentation allows each chip to use fewer metallization layers with mechanically stable dielectric materials, while the vertical stacking achieves the necessary interconnect density without relying on excessively thin or numerous low-k dielectric layers that would compromise mechanical stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances heat dissipation capabilities in stacked configurations, allowing for superior thermal management and performance comparable to single device configurations while maintaining high volume packing density.
Implementation Method 1
providing an active heat transfer system... in the form of a Peltier element... which may be implemented with an appropriate configuration so as to provide an overall superior thermally conductive path within the stacked device configuration
Data Source
AI summary
In a stacked semiconductor device, a Peltier element may be incorporated as a distributed element so as to provide active heat transfer from a high power device into a low power device, thereby achieving superior temperature control in stacked device configurations. For example, a CPU and a dynamic RAM device may be provided as a stacked configuration, wherein waste heat of the CPU may be efficiently distributed into the low power memory device.