Stacked Semiconductor Device with Vertical Peripheral Circuit Integration
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Solution Overview
Problem
The challenge in semiconductor technology is to enhance the storage density of semiconductor devices like DRAMs, optimize their comprehensive performance, and reduce fabrication costs.
Innovation Solution
A semiconductor device is designed with a first semiconductor structure and a second semiconductor structure in direct contact, where the second structure comprises a plurality of memory cells. The first semiconductor structure includes a peripheral circuit connected with the memory cells, with at least a portion of the peripheral circuit located directly below the memory cells. This configuration includes driving and sensing structures, interconnect structures, and a power layer to optimize connectivity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the peripheral circuit is disposed beside the memory cells in the conventional layout, then the circuit connectivity is maintained, but the storage density is reduced and parasitic capacitance increases due to longer connecting wire lengths
Solution Approach 1:
The peripheral circuit is moved from a lateral arrangement beside the memory cells to a vertical arrangement directly below the memory cells in the stacking direction. This dimensional change allows the memory cells to be disposed directly above the peripheral circuit, shortening the connecting wire lengths and reducing parasitic capacitance while maintaining circuit connectivity, thereby increasing storage density without excessive layout complexity
Solution Approach 2:
The memory cells and peripheral circuit are merged into a single integrated semiconductor structure through direct contact between the first semiconductor structure (peripheral circuit) and second semiconductor structure (memory cells). This integration eliminates the need for separate lateral arrangements and reduces the overall device footprint, improving storage density while managing layout complexity
2Reliability
If the connecting wire length between peripheral circuit and memory cells is reduced, then parasitic capacitance is reduced and sensing tolerance is improved, but the layout flexibility is constrained
Solution Approach 1:
The connection between peripheral circuit and memory cells transitions from lateral wiring to vertical stacking, dramatically reducing wire length and parasitic capacitance to improve sensing tolerance. The standardized interface between the first and second semiconductor structures maintains layout flexibility for different device configurations
Solution Approach 2:
The peripheral circuit structure is designed with universal interfaces that can connect to various memory cell configurations. The first semiconductor structure with peripheral circuit serves as a standardized base that can support different second semiconductor structure arrangements, maintaining adaptability while achieving short connection lengths through vertical integration
Data Source
AI summary
Implementations of the present application provide a semiconductor device, a fabrication method thereof and a memory system. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The second semiconductor structure is disposed on a side of the first semiconductor structure in the first direction and in direct contact with the first semiconductor structure, wherein the second semiconductor structure includes a plurality of memory cells, the first semiconductor structure includes a first peripheral circuit connected with the plurality of memory cells, and in the plane perpendicular to the first direction, at least a portion of the first peripheral circuit is located directly below the plurality of memory cells, wherein the first peripheral circuit includes at least one of a driving structure and a sensing structure.