Stacked Semiconductor Power Routing With Backside TSV and TDV Separation
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Solution Overview
Problem
The complexity of trace routing between stacked dies in semiconductor packaging due to dense trace arrangements and the need to protect data and control signals from power signal interference poses a challenge in achieving greater computation capability with lower power consumption.
Innovation Solution
A semiconductor structure with a backside redistribution layer (RDL), through dielectric vias (TDVs), and through silicon vias (TSVs) allows for backside power delivery, enabling more flexible trace routing by separating power signal paths from data and control signal paths, thereby increasing computation power within a smaller area with reduced power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traces are arranged densely within a limited area in die-stacking structure, then computation capability per area is improved, but trace routing complexity increases
Solution Approach 1:
The patent introduces a backside RDL layer, transitioning from a single-plane trace routing to a multi-dimensional structure. This allows traces to be routed on both the front and back sides of the die stack, effectively adding a new dimension for trace arrangement and reducing routing complexity on the front side while maintaining high density.
Solution Approach 2:
The patent divides the trace routing function into separate layers: front RDL for signal routing and backside RDL for power delivery. This segmentation allows independent optimization of signal and power paths, simplifying the overall routing complexity while enabling dense arrangement of computation-critical signal traces.
2Device complexity
If power signals and data/control signals are routed together, then routing complexity is reduced, but signal interference increases
Solution Approach 1:
The patent segments power signal routing from data/control signal routing by implementing a backside RDL dedicated to power delivery, while the front RDL handles signal traces. This physical separation eliminates electromagnetic interference between power and signal traces while maintaining routing efficiency through specialized pathways for each signal type.
3Productivity
If dies are stacked to increase computation capability, then area efficiency is improved, but trace routing difficulty increases
Solution Approach 1:
By implementing a backside RDL structure, the patent adds a second routing plane to the die-stack architecture. This dimensional expansion provides additional routing resources that scale with the number of stacked dies, enabling efficient trace routing even as computation capability increases through additional die layers.
Solution Approach 2:
The backside RDL acts as an intermediary layer that facilitates power and signal distribution across multiple stacked dies. It serves as a mediation structure that simplifies the connection between bumps on the die stack and the TSVs/through-die vias, making the overall routing process more manageable despite the increased complexity of multi-die stacking.
Data Source
AI summary
The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.