Stacked Semiconductor Power Wiring Reduces Self-Inductance
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Solution Overview
Problem
Conventional stacked semiconductor devices face challenges in reducing self-inductance of power supply wiring, which affects the quality of power supply and signal processing operations, especially due to bent wiring paths and uneven land configurations on printed wiring boards, leading to increased inductance and noise propagation.
Innovation Solution
The solution involves a stacked semiconductor device configuration with a first semiconductor package and a second semiconductor package stacked through a solder joint, featuring a power supply pattern with a larger number of input lands connected in parallel to reduce self-inductance, and independent power supply and ground wiring paths to prevent noise propagation, while maintaining the wiring capability of the motherboard.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the power supply wiring path is bent to avoid the first semiconductor element and accommodate unequal land intervals, then the mounting area is reduced and stacking is enabled, but the self-inductance of the power supply wiring increases
Solution Approach 1:
The power supply wiring is divided into multiple segments: a first power supply wiring in the lower first printed wiring board, a second power supply wiring in the upper second printed wiring board, and connection conductors connecting them. This segmentation allows each segment to be optimized independently - the first wiring can be routed to avoid the semiconductor element, while the second wiring can be positioned to minimize inductance, and the connection conductors can be arranged to reduce overall inductance through proper spacing and configuration.
Solution Approach 2:
The solution moves from a two-dimensional planar wiring problem to a three-dimensional stacked configuration. By utilizing vertical stacking with multiple layers and boards, the wiring paths can be arranged in different spatial dimensions, allowing the power supply wiring to connect input and output lands through multiple layers without being constrained to a single bent path on one board, thereby reducing self-inductance while maintaining compact mounting area.
2Reliability
If multiple power supply connection conductors and ground connection conductors are arranged adjacently to decrease self-inductance and increase mutual inductance, then the inductance is reduced, but the device complexity increases
Solution Approach 1:
The invention extracts and separates the power supply connection conductors and ground connection conductors into distinct, independently optimized groups. Rather than densely intermixing them, the connection conductors are positioned to connect corresponding lands between boards, while ground conductors are arranged to provide stable reference potentials. This separation simplifies the wiring configuration while achieving low inductance through proper spatial arrangement and reduced interference.
Data Source
AI summary
An interposer of a first semiconductor package includes a power supply wiring for a second semiconductor element, the power supply wiring including a land provided in one surface layer, and a power supply pattern provided in an inner layer and electrically connected to the land, the power supply wiring further including a larger number of lands than the land, which are provided in another surface layer and electrically connected in parallel to the power supply pattern. In a stacked semiconductor device, this configuration can improve the quality of power supply to the second semiconductor element to secure signal processing operation while preventing an increase in inductance caused by the bending of a power supply path in a power supply wiring of a printed wiring board or by a deviation of connection intervals.