Stacked Semiconductor Interconnects via Ring-Shaped Hard Mask
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller form factors, higher integration density, and lower power consumption as demand increases for miniaturization, higher speed, and greater bandwidth, which existing packaging techniques struggle to address effectively.
Innovation Solution
The method involves forming stacked semiconductor devices by bonding two semiconductor wafers using direct bonding techniques, creating interconnect structures with conductive plugs that connect active circuits across the wafers, reducing the form factor and power consumption while increasing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional packaging techniques are used, then manufacturing processes remain simple, but integration density cannot be increased and form factor cannot be reduced
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked packaging, bonding semiconductor wafers vertically to achieve higher integration density. Multiple active circuits are stacked in the Z-direction, enabling more components per unit area without increasing planar footprint.
Solution Approach 2:
The patent divides the semiconductor device into multiple separate wafers that are bonded together in a stack. Each wafer contains specific active circuits, and the segmentation allows independent fabrication and optimization of each layer while achieving high overall integration density.
2Volume of moving object
If semiconductor wafers are stacked to reduce form factor, then device size decreases, but bonding process complexity increases
Solution Approach 1:
The patent employs self-aligned bonding where corresponding bonding pads on adjacent wafers automatically align during the bonding process. This self-alignment mechanism eliminates the need for complex external alignment systems and reduces bonding process complexity despite the three-dimensional stacking.
Solution Approach 2:
The patent uses bonding pads as intermediary elements that facilitate wafer bonding. These pads serve as both electrical connection points and alignment references, simplifying the bonding process by providing a standardized interface between stacked wafers.
3Reliability
If direct bonding is used to connect wafers, then electrical connections are established, but parasitic interference increases
Solution Approach 1:
The patent extracts the bonding pad structure from the substrate and forms it as a separate, suspended element above the substrate surface. This extraction removes the bonding pad from direct contact with the substrate, reducing parasitic capacitance and interference while maintaining reliable electrical connections through the interconnect structure.
Solution Approach 2:
The patent employs curved or rounded interconnect structures that transition smoothly between bonding pads and substrate contacts. These curved paths reduce sharp corners and edges that would concentrate electric fields, thereby minimizing parasitic effects and interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher integration density, smaller form factors, cost-effectiveness, and reduced power consumption by establishing efficient electrical connections between stacked semiconductor wafers, enhancing performance and reducing parasitic interference.
Implementation Method 1
The commonly used bonding techniques include direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermo-compressive bonding, reactive bonding and/or the like.
Data Source
AI summary
An apparatus comprises a first semiconductor chip including a first substrate, a plurality of first inter-metal dielectric layers and a plurality of first metal lines, a second semiconductor chip having a surface in contact with a surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second inter-metal dielectric layers and a plurality of second metal lines and a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion over a first side of a hard mask layer and a second portion over a second side of the hard mask layer, wherein the hard mask layer is a ring-shaped layer, and wherein the conductive plug is formed in a center opening of the ring-shaped layer.