Stacked Semiconductor Device with Overlapping Sense Amplifier
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Solution Overview
Problem
Dynamic random access memory (DRAM) faces challenges in increasing capacity due to the limited reduction in memory cell size and the area occupied by sense amplifiers, which hinder the miniaturization and power efficiency of DRAM devices.
Innovation Solution
A semiconductor device design that includes a memory circuit and an amplifier circuit with overlapping regions separated by an insulating layer, utilizing single crystal and oxide semiconductors to reduce area and power consumption while maintaining high-speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the sense amplifier is provided between memory cell arrays, then the area of the sense amplifier region is reduced, but the installation area for the memory cell arrays is limited and the increase in capacity is hindered
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture. The sense amplifier is positioned on a different layer (third layer) above the memory cell array (first layer), with an insulating layer separating them. This vertical stacking enables both the sense amplifier region area reduction and memory capacity increase to coexist, as the memory cell arrays can be expanded in the horizontal plane without conflicting with the sense amplifier placement.
2Productivity
If the memory cell size is reduced and elements are miniaturized, then the capacity of DRAM increases, but the reduction has limits and further increase becomes technically difficult
Solution Approach 1:
By stacking the sense amplifier above the memory cell array using an insulating layer, the patent frees up horizontal space that can be used to increase the number of memory cell arrays or expand their size, thereby increasing capacity without further miniaturizing individual elements beyond their practical limits.
3Reliability
If the sense amplifier occupies a certain area, then the area of the region where the memory cell is provided is limited, but the sense amplifier is necessary for data reading
Solution Approach 1:
The patent positions the sense amplifier on a higher layer (third layer) above the memory cell array (first layer), separated by an insulating layer. This vertical separation allows the sense amplifier to perform its necessary data reading function while occupying minimal horizontal space, thereby maximizing the area available for memory cell arrays.
4Use of energy by stationary object
If conventional semiconductor structures are used, then the device area and power consumption are high, but novel structures are needed to reduce these parameters
Solution Approach 1:
The stacked structure with the sense amplifier positioned above the memory cell array reduces the horizontal footprint of the device. This area reduction directly contributes to lower power consumption, as smaller devices require less energy for operation. The insulating layer enables this vertical integration while maintaining electrical isolation.
Data Source
AI summary
Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.