Stacked Semiconductor Device Shared Bumps Signal Transfer
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Solution Overview
Problem
As LSIs are miniaturized, the increasing manufacturing cost and chip area due to the large number of chip-to-chip electrodes required for signal transfer between processor and memory chips lead to signal delay and increased power consumption, making it difficult to enhance performance effectively.
Innovation Solution
A semiconductor device with a processor chip and a memory chip stacked using shared bumps for address and data transfer, where control signals are transferred via dedicated chip-to-chip electrodes, reducing the overall number of electrodes and arranging them in a cross-shaped region of the memory logic unit to minimize signal delay and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large number of chip-to-chip electrodes are used to transfer signals between processor and memory chips, then signal transfer capability is improved, but chip area increases and manufacturing cost increases
Solution Approach 1:
The patent combines multiple signal functions into shared electrodes. Specifically, the same electrodes are used for both address signal transfer and data signal transfer at different time periods, merging what would traditionally require separate dedicated electrode paths into a single shared resource, thereby reducing the total number of electrodes needed.
Solution Approach 2:
The electrodes are designed to serve multiple functions: they can transfer address signals during one time period and data signals during another time period. This multi-functionality allows the same physical electrodes to handle different types of signal transfer operations, reducing the overall electrode count while maintaining full signal transfer capability.
2Reliability
If a large number of chip-to-chip electrodes are used to transfer signals between processor and memory chips, then signal transfer capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple signal functions into shared electrodes. Specifically, the same electrodes are used for both address signal transfer and data signal transfer at different time periods, merging what would traditionally require separate dedicated electrode paths into a single shared resource, thereby reducing the total number of electrodes needed.
Solution Approach 2:
The electrodes are designed to serve multiple functions: they can transfer address signals during one time period and data signals during another time period. This multi-functionality allows the same physical electrodes to handle different types of signal transfer operations, reducing the overall electrode count while maintaining full signal transfer capability.
3Reliability
If long interconnects are used to connect bus to chip-to-chip electrodes, then signal transfer capability is improved, but signal delay increases and power consumption increases
Solution Approach 1:
The patent transitions from a planar interconnect layout to a three-dimensional stacked architecture. By stacking the memory chip directly on the processor chip with electrodes positioned at the interface, the signal path is shortened from extending across a large chip area to a direct vertical connection, dramatically reducing interconnect length and signal delay.
4Reliability
If long interconnects are used to connect bus to chip-to-chip electrodes, then signal transfer capability is improved, but power consumption increases
Solution Approach 1:
The patent transitions from a planar interconnect layout to a three-dimensional stacked architecture. By stacking the memory chip directly on the processor chip with electrodes positioned at the interface, the signal path is shortened from extending across a large chip area to a direct vertical connection, dramatically reducing interconnect length and signal delay.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit. An address and data are transferred between the processor chip and the memory chip by use of shared bumps of the bumps.