Stacked Semiconductor Package With Hybrid Bonding and Side Terminals
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Solution Overview
Problem
The electronics industry faces challenges in creating high-performance, high-speed, and miniaturized semiconductor packages with improved structural stability and electrical characteristics, while reducing manufacturing costs and size.
Innovation Solution
A semiconductor package design that includes a first and second semiconductor chip bonded together using a hybrid bonding process with insulating material, surrounded by an insulating layer, and connected via a redistribution substrate with an antenna pattern for enhanced electrical connectivity, allowing for miniaturization and improved thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are mounted on PCB with bonding wires or bumps, then electrical connection is achieved, but package size and weight increase
Solution Approach 1:
The patent merges the first and second semiconductor chips by forming a bonding layer that integrates them into a single package structure. The chips are mounted on different surfaces of the same substrate (first substrate for first chip, second substrate for second chip), eliminating the need for separate PCB mounting and reducing overall package size while maintaining reliable electrical connections through integrated interconnection structures.
Solution Approach 2:
The patent transitions from traditional planar mounting on PCB to a three-dimensional stacked configuration where chips are mounted on opposite surfaces of substrates. This dimensional change allows compact integration while maintaining electrical connectivity through vertical interconnection structures, thereby reducing package footprint without compromising connection reliability.
2Stability of the object's composition
If additional bonding members are used to connect semiconductor chips, then structural stability is improved, but package height increases
Solution Approach 1:
The patent eliminates additional bonding members by merging the semiconductor chips directly with the substrates through integrated mounting structures. The first chip is mounted on the first substrate and the second chip on the second substrate, with electrical and mechanical connections achieved through the substrate-integrated interconnection structures, thereby reducing package height while maintaining structural stability.
Solution Approach 2:
The substrates serve as intermediaries between the semiconductor chips and the external environment. The first substrate mediates the connection for the first chip, and the second substrate mediates the connection for the second chip, providing structural support and electrical connectivity without requiring additional bonding members, thus reducing package height while ensuring structural stability.
3Adaptability or versatility
If multiple semiconductor chips are integrated in a single package, then functionality is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the multi-chip package into distinct modules: first substrate with first chip, second substrate with second chip, and integrated interconnection structures. This segmentation allows each module to be manufactured and tested independently before final assembly, reducing overall manufacturing complexity while enabling enhanced functionality through multiple chips in a single package.
Solution Approach 2:
The substrates are designed with multi-functionality, serving as mechanical support, electrical interconnection, and thermal management structures simultaneously. This universal design reduces the number of separate components needed, simplifying the manufacturing process while enabling the integration of multiple semiconductor chips with enhanced functionality in a single package.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves improved structural stability, reduced package height, and enhanced electrical characteristics by bonding semiconductor chips without additional bonding members, enabling efficient heat dissipation and integration of multiple chips in a single package.
Implementation Method 1
an upper portion of the first wafer is oxidized or nitrified by the surface treatment process
Implementation Method 2
an upper portion of the first wafer is oxidized or nitrified by the surface treatment process
Implementation Method 3
bonding, the first and second bonding layers to each other by a hybrid bonding process performed by a surface activation process at an interface between the first and second bonding layers
Implementation Method 4
enabling efficient heat dissipation
Data Source
AI summary
A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a second semiconductor chip disposed on a top surface of the first semiconductor chip, an insulating layer surrounding the first and second semiconductor chips on the first redistribution substrate, a second redistribution substrate disposed on the second semiconductor chip and on which the second semiconductor chip is mounted, and a connection terminal disposed at a side of the first and second semiconductor chips and connected to the first and second redistribution substrates. An inactive surface of the second semiconductor chip is in contact with an inactive surface of the first semiconductor chip. At an interface of the first and second semiconductor chips, an upper portion of the first semiconductor chip and a lower portion of the second semiconductor chip constitute one body formed of a same material.