Sidewall Interconnection Layout for Dense Stacked Semiconductor Layers
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Solution Overview
Problem
The miniaturization of semiconductor elements poses challenges in manufacturing high-density interconnection structures, particularly in stacking multiple layers, where traditional methods struggle to provide flexible and efficient interconnections with low resistance and high bandwidth.
Innovation Solution
A semiconductor device with a sidewall interconnection structure is developed, featuring an electrical isolation layer and a conductive structure that allows for lateral connections between stacked semiconductor elements, reducing photolithography steps and manufacturing costs, and enabling three-dimensional interconnections with low resistance and high bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional interconnection methods are used for stacked semiconductor layers, then manufacturing process is simpler, but interconnection density and flexibility are insufficient
Solution Approach 1:
The patent transitions from planar interconnections to three-dimensional sidewall interconnections. Conductive structures are formed on the sidewalls of trenches between stacked element layers, enabling vertical and lateral connections simultaneously. This dimensional change allows interconnections to access multiple element layers at different heights, significantly increasing interconnection density and flexibility without proportionally increasing manufacturing complexity.
2Manufacturing precision
If more photolithography steps are used to create complex interconnections, then interconnection precision improves, but manufacturing cost increases
Solution Approach 1:
The mask layer serves multiple functions: it defines the pattern of conductive structures, protects underlying layers during etching, and enables self-alignment for subsequent processing steps. This multi-functional mask approach achieves precise sidewall interconnection formation without requiring additional specialized photolithography steps, thereby maintaining interconnection precision while controlling manufacturing costs.
3Quantity of substance
If semiconductor elements are miniaturized, then device density increases, but lateral space for interconnections decreases
Solution Approach 1:
The patent utilizes the vertical dimension by forming conductive structures on the sidewalls of trenches between stacked layers. This allows interconnections to extend vertically along the sidewalls and access elements at different heights, effectively converting limited lateral space into three-dimensional connection pathways. The sidewall interconnection structure enables high-density interconnections without requiring additional lateral area, thus resolving the space constraint imposed by element miniaturization.
Data Source
AI summary
A semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device are provided. The semiconductor device may include: a plurality of element stacks, wherein each element stack includes a plurality of stacked layers of semiconductor elements, each semiconductor element includes a gate electrode and source/drain regions on opposite sides of the gate electrode; and an interconnection structure between the plurality of element stacks. The interconnection structure includes an electrical isolation layer, and a conductive structure in the electrical isolation layer. At least one of the gate electrode and the source/drain regions of each of at least a part of the semiconductor elements is in contact with and therefore electrically connected to the conductive structure of the interconnection structure at a corresponding height in a lateral direction.