Stacked Semiconductor Packaging With Conformal Stepped Interconnects
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Solution Overview
Problem
Conventional semiconductor packages face issues of high cost, decreased reliability, and large size, leading to suboptimal performance.
Innovation Solution
A packaged electronic device with a stacked semiconductor device structure featuring offset-stacked semiconductor dies and conformal conductive interconnects that follow a stepped profile, allowing for thinner profiles and flexible interconnect configurations, formed using techniques such as 3D printing or masked plating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packages are used, then manufacturing cost is reduced, but reliability decreases and performance is limited
Solution Approach 1:
The patent transitions from planar interconnect layouts to three-dimensional conformal interconnect structures that wrap around semiconductor devices. This dimensional change enables shorter interconnect paths and better signal integrity while maintaining manufacturing feasibility through advanced deposition techniques
Solution Approach 2:
The interconnect structures are designed with locally optimized properties, including varying thickness and material composition in different regions to match specific electrical and mechanical requirements. This allows high reliability in critical areas while controlling overall manufacturing complexity
2Productivity
If conventional package sizes are used, then manufacturing is simplified, but device performance decreases
Solution Approach 1:
The patent employs three-dimensional stacked architectures with multiple semiconductor devices vertically integrated. This enables higher device density and improved performance while the conformal interconnects provide systematic routing that manages the inherent complexity
Solution Approach 2:
The package structure implements nested configurations where smaller devices are integrated within larger package footprints, and interconnect layers are nested around device structures. This maximizes space utilization and performance while organizing complexity in a hierarchical manner
3Volume of moving object
If thicker profiles are used, then manufacturing is easier, but device size becomes too large
Solution Approach 1:
The patent adopts vertical stacking to reduce the lateral footprint of the package. By arranging devices and interconnects in the vertical dimension rather than spreading them out laterally, the package achieves compact size while maintaining manufacturability through standardized vertical processing steps
Solution Approach 2:
The conformal interconnect structures are implemented as thin film layers that conformally coat device surfaces. These thin film interconnects provide sufficient electrical performance while minimizing the vertical profile, enabling compact overall package dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables thinner, more reliable, and cost-effective semiconductor packages with improved interconnect reliability and flexibility, supporting complex configurations.
Implementation Method 1
conductive interconnect structures comprising a conformal layer that substantially conforms to the stepped profile
Data Source
AI summary
A packaged semiconductor device includes a substrate with first and second opposing major surfaces. A stacked semiconductor device structure is connected to the first major surface and includes a plurality of semiconductor die having terminals. Conductive interconnect structures electrically connect the terminals of the semiconductor dies together. The semiconductor dies are stacked together so that the terminals are exposed, and the stacked semiconductor device structure comprises a stepped profile. The conductive interconnect structures comprise a conformal layer that substantially follows the stepped profile.