Stacked Semiconductor Interconnects for Sub-100 Nm Heterogeneous Integration
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Solution Overview
Problem
Traditional IC design trends to pack more transistors on a monolithic die or system-on-chip (SoC) face challenges in integrating analog, logic, and memory circuits, leading to difficult chip scaling and increased costs.
Innovation Solution
Heterogeneous integration of separately manufactured semiconductor devices with stacked configurations, utilizing interconnect wiring structures and through-silicon vias (TSVs) to achieve contact pitches less than 100 nm, enabling enhanced functionality and improved operating characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more transistors are packed on a monolithic die or SoC, then transistor density increases, but chip scaling becomes difficult and costs increase
Solution Approach 1:
The patent divides the semiconductor system into multiple separate devices (logic device, memory device, analog device) that are manufactured independently and then stacked together. This segmentation allows each device to be optimized separately while achieving high overall transistor density in the stacked configuration, avoiding the scaling difficulties of monolithic integration.
Solution Approach 2:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking. By stacking multiple semiconductor devices vertically with interconnect wiring structures between them, the system achieves higher transistor density without further shrinking feature sizes, effectively moving the integration problem into the third dimension.
2Adaptability or versatility
If heterogeneous integration is used to integrate separately manufactured components, then functionality is enhanced and yield is improved, but interconnect wiring complexity increases
Solution Approach 1:
The patent uses vertical stacking to organize interconnect wiring structures in the third dimension, with first interconnect wiring over the first device, second interconnect wiring under the second device, and through-silicon vias connecting through the substrate. This vertical arrangement manages wiring complexity more efficiently than planar routing.
Solution Approach 2:
The patent introduces interconnect wiring structures as intermediary elements between the stacked semiconductor devices. These interconnect structures, including through-silicon vias, serve as mediators that enable electrical connections between separately manufactured devices while managing the complexity of heterogeneous integration.
3Quantity of substance
If contact pitch is reduced to less than 100 nm, then integration density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent achieves high integration density by stacking multiple semiconductor devices vertically, which allows for reduced contact pitch (less than 100 nm) between devices in the stack. The vertical arrangement enables dense interconnections through through-silicon vias and interconnect wiring structures without requiring extremely precise lateral alignment across large chip areas.
Data Source
AI summary
An approach for forming semiconductor structure composed of one or more stacked semiconductor devices with a first semiconductor device on a substrate, a first interconnect wiring structure over the first semiconductor device, a second interconnect wiring structure under a second semiconductor device joined to the first interconnect wiring structure, and a third interconnect wiring structure on the second semiconductor device where the first semiconductor device and the second semiconductor device are each one of a memory device or a logic device. The approach includes each of the first interconnect wiring structure, the second interconnect wiring structure, and the third interconnect wiring structure with a contact pitch to the first semiconductor device and to both sides of the second semiconductor device that is less than one hundred nanometers.