Stacked Semiconductor Substrates with Relay Electrode Pads
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Solution Overview
Problem
Conventional semiconductor device packaging methods, such as chip scale packaging, face challenges in miniaturization and area efficiency, particularly for standardized electronic devices like SD and micro SD memory cards, due to the need for aligned connection electrode pads and complex wiring structures, which restrict flexibility in lamination and increase production complexity.
Innovation Solution
A semiconductor device with a laminate structure where upper and lower semiconductor substrates are laminated with exposed relay electrode pads connected by wires, allowing for flexible displacement and reduced area occupation, and a method involving inkjet deposition of conductive ink to form wires and insulation layers, enabling efficient connection and reduced mechanical stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If connection electrode pads are arranged in a single direction for simplified wiring, then device complexity is reduced, but the area occupied by laminated semiconductor chips is extended
Solution Approach 1:
The invention transitions from single-direction linear arrangement to two-dimensional grid arrangement of connection electrode pads. This allows wires to connect pads in both horizontal and vertical directions, creating a mesh-like wiring structure that reduces the linear extension area while maintaining connectivity. The grid pattern enables more efficient space utilization compared to sequential single-direction stacking.
Solution Approach 2:
The invention pre-arranges connection electrode pads in a grid pattern on each semiconductor chip before lamination. This preliminary positioning allows subsequent wires to connect adjacent chips in multiple directions without requiring complex routing adjustments, thereby reducing the overall mounting area while maintaining simplified wiring connectivity.
2Ease of manufacture
If semiconductor chips are laminated in a stepped shape with deviation, then wiring connections are simplified, but the area occupied by the laminate is extended
Solution Approach 1:
The invention changes from one-dimensional stepped lamination to two-dimensional grid-based lamination where chips are arranged and connected in both horizontal and vertical directions. This allows the laminate to utilize area more efficiently, reducing the overall footprint while maintaining the simplicity of wire connections through the grid structure.
Solution Approach 2:
The invention merges multiple wiring paths in both horizontal and vertical directions into a unified grid connection system. This consolidation allows adjacent semiconductor chips to share common wire routes and connection points, reducing the total area required compared to separate single-direction wiring paths.
3Area of stationary object
If upper semiconductor chips are directly mounted without deviation, then mounting area is reduced, but connection electrode pads are covered and wiring becomes complex
Solution Approach 1:
The invention enables direct mounting of upper chips without deviation by implementing two-dimensional grid wiring that can route connections in both horizontal and vertical directions. This multi-directional wiring capability allows pads to be connected even when covered by overlapping chips, eliminating the need for stepped arrangements while maintaining area efficiency.
Solution Approach 2:
The invention introduces relay electrode pads as intermediary connection points that facilitate wiring through covered areas. These relay pads act as mediators that receive signals from lower chips and transmit them to upper chips, enabling connections without requiring direct line-of-sight access to all electrode pads.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for a more compact laminate structure, facilitating the mounting of multiple semiconductor chips on limited areas and simplifying the production process by reducing the area occupied by the semiconductor substrates and minimizing mechanical stress on wires, thus enhancing area efficiency and production flexibility.
Implementation Method 1
liquid droplets of conductive ink are discharged in a manner so as to connect the connection electrode pads P to the substrate terminals BP
Implementation Method 2
the discharged ink is dried and fired
Implementation Method 3
the discharged ink is dried and fired
Data Source
AI summary
A semiconductor device includes: a plurality of semiconductor substrates each having a pad-formed surface and being mutually laminated; a connection electrode pad formed on the pad-formed surface; a wire connecting the connection electrode pads of the plurality of semiconductor substrates so as to electrically connect the semiconductor substrates; a relay electrode pad that is provided on the pad-formed surface of a lower one of the laminated semiconductor substrates so as to be exposed by an upper one of the laminated semiconductor substrates, and that is connected to the connection electrode pad by a relay wire included in the wire; and a mounting electrode pad that is formed on a mounting surface on which the laminated semiconductor substrates are mounted, and that is connected to the relay electrode pad of the lower semiconductor substrate by the wire. In the device, the wire electrically connects the connection electrode pad of the upper semiconductor substrate to the relay electrode pad of the lower semiconductor substrate.