Stacked Semiconductor Substrates Using Through-Silicon Vias
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) require increasing numbers of input/output pins due to miniaturization and complexity, leading to higher design and manufacturing costs, especially for connecting to configuration random access memory (CRAM) and external circuitry.
Innovation Solution
A semiconductor system where multiple substrates are stacked or mounted side-by-side with through-silicon-vias and redistribution layers to reduce the need for external input/output ports, utilizing pre-existing circuit designs and adding vias to the periphery of integrated circuits for efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of input/output pins is increased to meet the requirements of faster and more complicated integrated circuits, then the functionality and performance of the circuits are improved, but the design and manufacturing costs increase
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of circuits to a three-dimensional stacked configuration. Multiple integrated circuits are vertically stacked and interconnected through through-silicon vias, allowing increased functionality without proportionally increasing package footprint or I/O pin count. This dimensional change enables more circuits to be integrated within the same package area.
Solution Approach 2:
The patent implements a nested structure where multiple integrated circuits are stacked one above another, with smaller circuits positioned within or between larger circuits. The through-silicon vias penetrate through the substrates to connect upper and lower circuits, creating a compact nested arrangement that maximizes space utilization and reduces the number of external I/O pins required.
2Adaptability or versatility
If more input/output pins are used to connect FPGAs to external circuitry and CRAM, then the connectivity is improved, but the manufacturing cost increases
Solution Approach 1:
The patent moves connectivity from a two-dimensional surface connection to a three-dimensional vertical interconnection scheme. Through-silicon vias provide direct vertical pathways between stacked circuits, reducing the need for extensive external I/O pins and trace routing, thereby simplifying manufacturing while maintaining high connectivity.
Solution Approach 2:
The patent introduces through-silicon vias as intermediary connection elements that facilitate electrical connections between stacked integrated circuits. These vias act as mediators, enabling direct communication between upper and lower circuits without requiring external I/O pins, thus reducing manufacturing complexity and cost.
3Area of moving object
If integrated circuits are miniaturized to reduce package size, then the space efficiency is improved, but the number of input/output pins required increases
Solution Approach 1:
The patent addresses the I/O pin increase by stacking miniaturized circuits vertically. The through-silicon vias provide compact interconnections between layers, allowing high-density integration without proportionally increasing the number of external I/O pins. The three-dimensional arrangement efficiently utilizes package volume while controlling I/O requirements.
Solution Approach 2:
The patent employs nested stacking of miniaturized circuits where multiple small circuits are vertically arranged and interconnected through through-silicon vias. This nesting approach maximizes the use of package volume, allowing more functionality to be packed into a smaller footprint without linearly increasing external I/O pin count.
Data Source
AI summary
A semiconductor system in a package in which at least first and second semiconductor substrates are mounted one above the other on a package substrate. The first substrate is mounted on the package substrate with its active (or front) side facing the package substrate. A plurality of through-silicon-vias (TSVs) extend through one or more peripheral regions of the first substrate; and a redistribution layer is located on the back side of the first substrate and connected to the TSVs. The second substrate is mounted on the first substrate and electrically connected to circuits in the active side of the first substrate through the redistribution layer and the TSVs. Illustratively, one of the substrates is an FPGA and one or more of the other substrates stores the configuration memory and/or other functional memory for the FPGA.