Stacked Semiconductor Devices with Embedded Test Pads
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Solution Overview
Problem
The semiconductor industry faces challenges in efficiently testing and identifying known good stacks (KGSs) and known bad stacks (KBSs) during the stacking process of semiconductor devices, leading to increased manufacturing costs and reduced yield due to the need for separate testing of individual dies before assembly.
Innovation Solution
The implementation of embedded test pads on integrated fan-out (InFO) devices allows for electronic functional testing (E-test) after each stacking step, enabling the identification and reworking of KBSs, thus limiting further processing to only KGSs, and using dummy workpieces to maintain uniform form factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate testing of individual dies is performed before assembly, then testing reliability is improved, but manufacturing cost increases and productivity decreases
Solution Approach 1:
The patent merges individual die testing with stack-level testing by implementing test pads on the interposer that can access and test multiple dies simultaneously. This allows testing to be performed at the stack level rather than requiring separate testing of each die before assembly, thereby improving productivity while maintaining testing reliability through comprehensive stack-level verification.
Solution Approach 2:
The interposer serves as an intermediary structure that provides test pads accessible from the rear surface, enabling testing signals to reach multiple dies through the stack without requiring front-side access. This intermediary testing mechanism allows efficient stack-level testing that reduces manufacturing steps while ensuring thorough testing coverage.
2Reliability
If separate testing of individual dies is performed before assembly, then defect identification is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple testing functions into a unified stack-level testing approach using test pads on the interposer. This merged testing method identifies defects in multiple dies simultaneously during stack assembly rather than requiring separate testing of each die, thereby reducing manufacturing cost while maintaining defect identification accuracy through comprehensive stack-level testing.
Solution Approach 2:
The patent introduces rear-side test pads on the interposer, accessing the testing function from a different dimensional perspective (rear side rather than front side). This allows testing signals to penetrate through the stack from the rear, enabling cost-effective stack-level testing that identifies defects without requiring expensive separate die-level testing infrastructure.
3Quantity of substance
If stacked semiconductor devices are formed with multiple workpieces, then integration density is improved, but complexity of testing and identification increases
Solution Approach 1:
The interposer acts as an intermediary structure with test pads positioned on its rear surface, providing a centralized access point for testing multiple stacked workpieces. This intermediary testing interface simplifies the testing process by allowing single-point access to all dies in the stack, thereby reducing testing complexity while maintaining high integration density through multi-workpiece stacking.
Solution Approach 2:
The test pads on the interposer serve universal testing functions for multiple different workpieces stacked together. A single test pad structure can test multiple dies simultaneously through the stack, providing multi-functionality that reduces testing complexity while supporting high integration density with multiple workpieces in the stack.
Data Source
AI summary
Stacked semiconductor devices and methods of forming the same are disclosed. First tier workpieces are mounted on a top surface of a semiconductor device to form first tier stacks, the semiconductor device comprising one or more integrated circuit dies, the semiconductor device having one or more test pads per integrated circuit die on the top surface of the semiconductor device. Each of the first tier stacks is electrically tested to identify first known good stacks and first known bad stacks. Second tier workpieces are mounted atop the first known good stacks, thereby forming second tier stacks. Each of the second tier stacks is electrically tested to identify second known good stacks and second known bad stacks. Stacking process further comprises one or more workpiece mounting/testing cycles. The stacking process continues until the stacked semiconductor devices comprise desired number of workpieces.