Stacked Semiconductor Package for Thermal Dissipation Stability
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving compactness, high thermal radiation efficiency, and structural stability, particularly when operating at high frequency signals, due to limitations in thermal dissipation and intermetallic compound formation.
Innovation Solution
A semiconductor package design featuring a stacked configuration with a lower and upper semiconductor chip, each surrounded by molding layers, and connected via posts and redistribution substrates, which enhances thermal radiation through the upper semiconductor chip's high thermal conductivity and prevents heat-induced intermetallic compound formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a plurality of semiconductor chips are mounted in a single package to reduce size and weight, then compactness is improved, but thermal dissipation becomes more difficult and thermal radiation efficiency deteriorates
Solution Approach 1:
The patent transitions from a planar arrangement of semiconductor chips to a three-dimensional stacked configuration. Multiple semiconductor chips are vertically stacked and connected through via structures, allowing heat to dissipate in the vertical dimension. This dimensional change enables compact packaging while maintaining effective thermal radiation pathways through the stacked architecture.
Solution Approach 2:
The patent divides the thermal management system into segmented pathways by providing multiple via structures distributed across the package. Each via structure creates an independent thermal conduction channel, segmenting the heat dissipation process into multiple parallel pathways that collectively improve thermal radiation efficiency while maintaining compact dimensions.
2Speed
If high frequency signals are used to achieve high performance, then operating speed is improved, but thermal dissipation becomes more difficult and intermetallic compound formation increases
Solution Approach 1:
The patent introduces via structures as intermediary thermal management elements between the semiconductor chips and the package substrate. These via structures serve as mediators that conduct heat away from the high-frequency operating chips, preventing excessive temperature rise that would otherwise accelerate intermetallic compound formation and degrade structural stability.
Solution Approach 2:
The patent implements preliminary thermal management by integrating via structures during the packaging process itself, rather than adding thermal management solutions after the chips are mounted. This preliminary action ensures that thermal dissipation pathways are established before heat accumulation can cause intermetallic compound formation, thereby maintaining structural stability during high-frequency operation.
3Temperature
If complex packaging structures are used to improve thermal radiation, then thermal management is improved, but manufacturing complexity and failure occurrence increase
Solution Approach 1:
The patent merges multiple functions into the via structures, which simultaneously serve as electrical interconnects between stacked semiconductor chips and as thermal conduction pathways for heat dissipation. This merging of electrical and thermal functions into a single structural element achieves effective thermal management without requiring separate complex thermal management systems, thereby reducing fabrication complexity and failure occurrence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves thermal radiation efficiency, increases structural stability, and simplifies the fabrication process by allowing for a high aspect ratio vertical connector, reducing the occurrence of failures and enhancing operating stability.
Implementation Method 1
the upper semiconductor chip's high thermal conductivity
Data Source
AI summary
Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a lower semiconductor chip on a first redistribution substrate and including a through via, a lower molding layer on the first redistribution substrate and surrounding the lower semiconductor chip, a lower post on the first redistribution substrate and laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and coupled to the through via, an upper molding layer on the lower molding layer and surrounding the upper semiconductor chip, an upper post on the lower molding layer and laterally spaced apart from the upper semiconductor chip, and a second redistribution substrate on the upper molding layer and coupled to the upper post. A top surface of the lower molding layer is at a level higher than that of a top surface of the lower semiconductor chip.