Stacked Semiconductor Interconnect Structure for Lower Thermal Stress
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and packaging techniques as demand increases for smaller, faster, and lower power consumption devices, with existing methods struggling to efficiently integrate and interconnect semiconductor dies while managing thermal expansion mismatches and reducing parasitic contributions from redistribution layers.
Innovation Solution
The development of stacked semiconductor devices involves forming semiconductor dies with a passivation layer, buffer layer, and routing structures that include conductive pillars and lines, which are then singulated and interconnected using redistribution layers to create a compact, efficient packaging solution that reduces thermal stress and parasitic contributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If semiconductor dies are stacked using through connections (TVs) to reduce footprint, then integration density improves, but thermal expansion mismatch between layers increases
Solution Approach 1:
The patent introduces an intermediary layer between stacked semiconductor dies that acts as a buffer to accommodate thermal expansion differences. This intermediary structure absorbs the stress caused by mismatched thermal expansion coefficients, preventing damage to the through connections while enabling compact stacking.
Solution Approach 2:
The patent modifies physical parameters of the interconnection structure, specifically changing the geometry and material properties of the through connections to accommodate thermal stress. By adjusting parameters such as connection flexibility and layer compliance, the structure can withstand thermal expansion mismatch while maintaining electrical connectivity.
2Reliability
If redistribution layers are added to interconnect stacked dies, then electrical connectivity improves, but parasitic contributions increase
Solution Approach 1:
The patent extracts or removes certain parasitic elements from the redistribution layer structure. By eliminating unnecessary conductive paths and optimizing the layout of interconnect lines, the design reduces capacitive and resistive parasitics while maintaining required electrical connectivity between stacked dies.
Solution Approach 2:
The patent transitions from planar redistribution layers to three-dimensional interconnection structures. By utilizing vertical through connections and立体 routing, the design achieves electrical connectivity without requiring extensive lateral redistribution, thereby reducing parasitic contributions from long interconnect paths.
3Area of moving object
If feature size is reduced to increase integration density, then component count per area improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent moves from two-dimensional planar integration to three-dimensional stacked integration. By utilizing the vertical dimension for additional components and interconnections, the design achieves higher integration density without continuously shrinking lateral feature sizes, thereby easing manufacturing precision requirements.
Data Source
AI summary
Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.