Stacked Semiconductor Device Through-Electrode Defect Detection
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Solution Overview
Problem
Existing semiconductor technologies face challenges in detecting defects in through-electrodes of stacked semiconductor devices, such as voids and cracks, which can lead to faulty electrical connections, necessitating a reliable testing method to identify and replace defective TSVs before packaging.
Innovation Solution
A stacked semiconductor device with a base die and core dies connected through through-electrodes, incorporating test circuits to transfer and compare test signals, allowing for the detection of defects in through-electrodes at the wafer level, ensuring normal operation before packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-electrodes are used to connect stacked semiconductor chips, then vertical electrical connection is achieved, but defects such as voids and cracks may occur causing faulty connections
Solution Approach 1:
The patent implements a test circuit that performs preliminary testing of through-electrodes at the wafer level before final packaging. The test circuit applies test signals through through-electrodes and compares returned signals to detect defects early, allowing corrective action before defective devices are packaged and distributed.
Solution Approach 2:
The patent introduces a reference through-electrode as an intermediary element that provides a known good reference path for comparison. The test circuit compares signals transmitted through target through-electrodes against the reference through-electrode to identify defects in the target electrodes without requiring complex external testing equipment.
2Productivity
If testing is performed after packaging, then device assembly is complete, but defect detection is delayed and corrective action is difficult
Solution Approach 1:
The test circuit is designed to operate at the wafer level before dicing and packaging, enabling preliminary defect detection when corrective action is still feasible. This preliminary testing approach maintains manufacturing efficiency by identifying defects early in the production flow rather than after packaging.
Solution Approach 2:
The test circuit is integrated directly into the semiconductor device structure, allowing the device to self-test its own through-electrodes. This self-service capability eliminates the need for complex external testing equipment and enables automated inline testing that maintains high manufacturing productivity.
3Measurement precision
If test circuits are added to verify through-electrode operation, then defect detection capability is improved, but device complexity increases
Solution Approach 1:
The test circuit utilizes existing device resources including through-electrodes, signal transmission paths, and basic circuit components to perform both normal device operation and self-testing functions. This multi-functionality approach enables defect detection without requiring completely separate dedicated testing hardware, thereby limiting the increase in device complexity.
Solution Approach 2:
The test circuit operates by changing the state or parameters of signal transmission through through-electrodes and comparing the changed parameters against reference values. This parameter-based testing approach achieves precise defect detection using simple comparison logic rather than complex measurement instrumentation.
4Productivity
If multiple core dies are stacked to increase integration, then device performance is improved, but the number of through-electrodes and potential defects increase
Solution Approach 1:
The patent segments the testing function by providing individual test capabilities for each through-electrode or group of through-electrodes. The test circuit can selectively test specific through-electrodes in the stacked device, allowing targeted defect detection in high-integration devices with multiple core dies and numerous through-electrodes without requiring testing of every single electrode simultaneously.
Data Source
AI summary
A stacked semiconductor device may include: a base die; and a plurality of core dies stacked over the base die and coupled to each other through a plurality of through-electrodes and a reference through-electrode, wherein the base die includes a first test circuit suitable for transferring a test oscillating signal to at least one target through-electrode among the through-electrodes, and outputting a test output signal by comparing a test base signal generated based on the test oscillating signal, with a test core signal transferred through the reference through-electrode, during a test operation; and wherein each of the core dies includes a second test circuit suitable for generating the test core signal corresponding to the test oscillating signal transferred through the target through-electrode, and transferring the test core signal to the reference through-electrode, during the test operation.