Stacked Semiconductor Package Through Electrode Signal Distribution
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Solution Overview
Problem
Existing stacked semiconductor packages face challenges in efficiently providing control signals and data signals to multiple semiconductor chips, limiting their high-speed data processing capabilities.
Innovation Solution
A stacked semiconductor package design that uses through electrodes to connect data bonding pads and chip selection pads, along with conductive wires to connect chip selection pads, allowing for high-speed data signal transmission and chip selection, while incorporating redistribution units and spacers for efficient signal distribution across multiple chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional signal distribution methods are used in stacked semiconductor packages, then device complexity is reduced, but data processing speed and signal transmission efficiency deteriorate
Solution Approach 1:
The patent segments the signal distribution function into two distinct pathways: through-electrode connections for high-speed data signals and wire connections for control signals. This segmentation allows each pathway to be optimized for its specific function, with through-electrodes providing direct high-speed data transmission and wires handling control signal distribution, thereby resolving the contradiction between speed and complexity.
Solution Approach 2:
The patent transitions from planar signal distribution to three-dimensional vertical distribution by implementing through-electrodes that penetrate multiple chip layers. This dimensional change enables direct vertical signal transmission between stacked chips, dramatically improving data processing speed while the modular wire connection system manages control signal complexity separately.
2Adaptability or versatility
If multiple control signals are provided to each chip through conventional wiring, then chip selection capability is improved, but fabrication time and manufacturing complexity increase
Solution Approach 1:
The wire connection system is designed to provide multiple control signals including chip selection signals, address signals, and other control functions through a unified wiring approach. This multi-functional wire system achieves comprehensive chip control capability while maintaining simpler fabrication processes compared to individual dedicated connections for each signal type.
3Speed
If through electrodes are used for data signal transmission, then data input/output speed is improved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent merges the data signal transmission function into the existing through-electrode structure that is already required for mechanical support and basic electrical connections in stacked chips. By combining data transmission with the structural through-electrodes, the patent achieves high-speed data I/O without adding separate complex transmission structures, thereby reducing overall device complexity.
4Quantity of substance
If conventional signal distribution is used in stacked chips, then manufacturing process is simplified, but data storage capacity and processing efficiency are limited
Solution Approach 1:
The patent segments the signal distribution network to dedicate through-electrodes exclusively for high-capacity data storage and processing connections, while separate wire connections handle control functions. This segmentation enables maximized data storage capacity through efficient vertical connections between stacked memory chips, while control signal complexity is managed independently through the wire system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-speed data input/output and reduces fabrication time by electrically connecting multiple semiconductor chips through through electrodes and conductive wires, enhancing data processing speed and storage capacity.
Implementation Method 1
through electrodes passing through the semiconductor chips and connected with the data bonding pads and the connection pad
Implementation Method 2
a conductive wire for connecting electrically the chip selection pad and the chip selection bonding pads
Implementation Method 3
The conductive connection member is a solder
Data Source
AI summary
A stacked semiconductor package provides an enhanced data storage capacity along with an improved data processing speed. The stacked semiconductor package includes a substrate having chip selection pads and a connection pad; a semiconductor chip module including a plurality of semiconductor chips including data bonding pads, a chip selection bonding pad, and data redistributions electrically connected with the data bonding pads and a data through electrode passing through the data bonding pad and connected with the data redistribution, the semiconductor chips being stacked so as to expose the chip selection bonding pad; and a conductive wire for connecting electrically the chip selection pad and the chip selection bonding pads.