3D Stacked Semiconductor Device With Through-Substrate Wiring
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Solution Overview
Problem
The challenge is to increase the number of memory cells in a semiconductor device without significantly increasing the size of the semiconductor chip as the number of stacked substrates increases, while maintaining efficient data storage and access.
Innovation Solution
The solution involves forming an operation circuit on the top surface of a semiconductor substrate, a memory array over the operation circuit, an inner pad group on an intermediate layer between the operation circuit and the memory array, and a wiring structure that passes through the substrate to couple the inner pad group to a first outer pad group on the bottom surface, allowing for efficient stacking and connection to a circuit board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked semiconductor substrates is increased to increase data storage capacity, then the number of memory cells increases, but the size of the semiconductor chip increases
Solution Approach 1:
The patent transitions from two-dimensional planar expansion to three-dimensional vertical stacking by forming multiple semiconductor substrates in the vertical direction. Memory cells are arranged across multiple stacked substrates (first, second, and third substrates) connected via through-substrate conductors, enabling capacity expansion along the vertical dimension rather than horizontal area expansion.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor substrates are stacked and interconnected. Each substrate contains memory cells and pad groups, with through-substrate conductors penetrating through stacked substrates to connect pad groups across different layers, creating a compact nested arrangement that maximizes storage density within a limited footprint.
2Ease of operation
If semiconductor substrates are stacked and offset from each other to expose pads for wire bonding, then pads can be accessed, but the device complexity increases
Solution Approach 1:
The patent extracts the pad grouping function into dedicated pad groups formed on each semiconductor substrate. These pad groups are positioned at specific locations and connected to memory cells through conductors within the substrate, separating the pad functionality from the memory cell array and enabling systematic interconnection across stacked substrates.
Solution Approach 2:
The patent divides the pad structure into multiple discrete pad groups (first pad group, second pad group, third pad group) located on different substrates. Each pad group is independently formed and connected to specific memory cells, allowing modular organization and simplified wire bonding operations compared to a single large pad structure.
Data Source
AI summary
A semiconductor device includes an operation circuit formed on a top surface of a semiconductor substrate, a memory array formed over the operation circuit, an inner pad group formed on an intermediate layer between the operation circuit and the memory array and coupled to the operation circuit, a first outer pad group formed on a bottom surface of the semiconductor substrate, and a wiring structure passing through the semiconductor substrate, and coupling the inner pad group to the first outer pad group.