Stacked Semiconductor Transistor Active Layer Design
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Solution Overview
Problem
The manufacturing process of transistors with complex active layers is highly difficult due to the intricate shape requirements, leading to larger transistor sizes and suboptimal display performance in display apparatuses.
Innovation Solution
A transistor design featuring a stacked active layer composed of multiple semiconductor patterns with different orthographic projections on the base, allowing for simpler manufacturing of each pattern and reducing the overall transistor size by minimizing the distance between them, along with a target insulating layer for electrical connectivity and a gate structure that enhances channel region length to improve switching efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complex active layer shape is used to improve transistor performance, then the display performance is improved, but the manufacturing difficulty increases significantly
Solution Approach 1:
The active layer is divided into multiple semiconductor patterns stacked in different layers. Each layer contains semiconductor patterns with simpler shapes that are easier to manufacture, while the stacked configuration collectively achieves the required complex functional performance. The orthographic projections of semiconductor patterns in different layers are different, allowing each layer to be optimized for manufacturability while contributing to the overall device performance.
2Productivity
If the active layer is designed with intricate shapes to enhance functionality, then the switching efficiency is improved, but the transistor size increases
Solution Approach 1:
The design transitions from a two-dimensional planar active layer to a three-dimensional stacked structure. By stacking semiconductor patterns in multiple layers with different orthographic projections, the effective channel length is extended vertically, improving switching efficiency without proportionally increasing the lateral footprint. This allows the transistor to achieve higher switching performance while maintaining a compact overall size.
3Ease of manufacture
If multiple semiconductor patterns are stacked with different orthographic projections, then the manufacturing process is simplified, but the electrical connectivity between layers becomes more challenging
Solution Approach 1:
An insulating layer is introduced between the semiconductor patterns of different layers. This insulating layer serves as an intermediary that enables electrical connectivity between layers through controlled conductive paths while maintaining isolation where needed. The insulating layer facilitates the formation of via holes or contact regions that connect the stacked semiconductor patterns, solving the connectivity challenge while preserving the manufacturing simplicity of the stacked structure.
Data Source
AI summary
Provided is a transistor, the transistor being located on a base and having an active layer, and the active layer of the transistor comprising a plurality of semiconductor patterns which are stacked, wherein the plurality of semiconductor patterns are electrically connected; and orthographic projections of any two of the semiconductor patterns on the base are different in shape. A method of manufacturing a transistor, a transistor device, and a display substrate and apparatus are also provided.