Stacked Semiconductor Transistors for High Integration and On-State Current
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration, high-speed operation, high definition, and high color reproducibility for applications in extended reality (XR) display apparatuses, while also requiring improved reliability, productivity, and on-state current performance.
Innovation Solution
The semiconductor device incorporates a first and second transistor structure with specific layer configurations, including conductive and semiconductor layers with different materials and insulating layers of varying film densities and nitrogen contents, allowing for precise channel length control and high on-state current, and employs a manufacturing method involving multiple film and layer processing steps to form stacked semiconductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the transistor size is reduced to achieve high integration, then the degree of integration is improved, but the on-state current and reliability deteriorate
Solution Approach 1:
The patent transitions from planar transistor structures to vertically stacked semiconductor layers, adding the vertical dimension to the device architecture. Multiple semiconductor layers are stacked above each other with conductive layers and insulating layers in between, creating a three-dimensional structure that increases integration density while preserving transistor performance through extended channel regions and improved electrical characteristics
Solution Approach 2:
The patent employs composite material structures with different semiconductor layers having distinct material compositions and properties. Each semiconductor layer can be made from different materials or doping configurations, allowing optimization of electrical characteristics, carrier mobility, and threshold voltage to maintain high on-state current despite miniaturization
2Productivity
If the transistor size is reduced to achieve high integration, then the degree of integration is improved, but the manufacturing precision deteriorates
Solution Approach 1:
The patent divides the transistor structure into multiple discrete stacked layers (semiconductor layers, conductive layers, insulating layers) that can be formed and aligned independently. Each layer is processed separately with defined interfaces, allowing precise control of layer thickness, composition, and positioning through sequential deposition and etching processes
Solution Approach 2:
The patent incorporates preliminary formation of insulating layers and conductive layers before final semiconductor layer stacking. These preliminary structures serve as alignment references and mechanical supports that facilitate precise positioning of subsequent layers, ensuring accurate registration even at reduced device dimensions
3Device complexity
If conventional transistor structures are used, then the device complexity is low, but the on-state current and high-speed operation capability deteriorate
Solution Approach 1:
The patent introduces vertical stacking of multiple semiconductor and conductive layers to create three-dimensional transistor structures. This vertical architecture extends the effective channel length and improves carrier transport pathways without increasing the planar footprint, enabling high on-state current and fast operation while maintaining compact device geometry
Solution Approach 2:
The patent uses composite semiconductor layer structures with different materials and doping profiles to optimize electrical characteristics. By combining layers with complementary properties (e.g., high mobility materials, doping-controlled layers), the transistor achieves superior on-state current and switching performance compared to conventional single-layer structures
Data Source
AI summary
A semiconductor device including a transistor having a minute size is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes first to third conductive layers, an insulating layer, and first and second semiconductor layers. The second conductive layer over the first conductive layer includes an opening overlapping with the first conductive layer. The first semiconductor layer is in contact with a top surface of the first conductive layer and a top surface and a side surface of the second conductive layer. The second semiconductor layer is in contact with a top surface of the first semiconductor layer. The insulating layer is in contact with a top surface of the second semiconductor layer. The third conductive layer overlaps with the first and second semiconductor layers in the opening. The second transistor includes the insulating layer, a third semiconductor layer, and fourth to sixth conductive layers. The fourth and fifth conductive layers are in contact with different top surfaces of the third semiconductor layer. Between the fourth semiconductor layer and the fifth semiconductor layer, the insulating layer is in contact with a top surface of the third semiconductor layer. The sixth conductive layer is in contact with a top surface of the insulating layer. The first and second semiconductor layers contain different materials. The second and third semiconductor layer contain the same material.