Stacked Semiconductor Trench Bonding for Overlay Alignment

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Solution Overview

Problem

Current semiconductor bonding processes face challenges in achieving uniformity of trench depth and width across multiple substrates, leading to issues with control and precision, particularly in stacked semiconductor devices where multi-step etching can result in poor control of trench depths and openings, causing overlay shifts and deviations in thickness.

Innovation Solution

The method involves forming trench arrays in each substrate before bonding, using etching processes to ensure homogeneous sizes and depths, and then bonding subsequent substrates with silicon-containing dielectric bonding layers, followed by thermal treatment to strengthen the bonds, allowing for precise alignment and reduced overlay shifts between trench arrays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multi-step etching is used to form trench arrays in stacked substrates, then trench depth and width can be adjusted, but control precision and uniformity of trench dimensions deteriorate

Engineering Contradiction:
Improvetrench depth and width adjustmentVSAvoidtrench dimension uniformity
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent forms trench arrays in each substrate before bonding the substrates together. This preliminary action ensures that each substrate has precisely controlled trench dimensions independently, avoiding the cumulative errors that occur with multi-step etching after bonding. The trenches are created with exact depth and width specifications before the substrates are joined, guaranteeing uniformity across the stacked device.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If substrates are bonded before forming trench arrays, then the bonding process can be simplified, but overlay shifts between trench arrays increase

Engineering Contradiction:
Improvebonding process simplicityVSAvoidoverlay alignment
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent forms trench arrays in each substrate before bonding, establishing precise trench positions and dimensions in advance. This preliminary formation of trenches with exact specifications ensures that when substrates are bonded, the trench arrays align perfectly with minimal overlay shifts, maintaining high manufacturing precision despite the added process step.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If conventional bonding processes are used without preliminary trench formation, then the manufacturing process is shorter, but trench depth and width uniformity across substrates deteriorates

Engineering Contradiction:
Improvemanufacturing process lengthVSAvoidtrench depth and width uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent forms trench arrays in each substrate before bonding the substrates together. This preliminary action ensures that each substrate has precisely controlled trench dimensions independently, avoiding the cumulative errors that occur with multi-step etching after bonding. The trenches are created with exact depth and width specifications before the substrates are joined, guaranteeing uniformity across the stacked device.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of semiconductor devices with reduced overlay shifts between trench arrays, improving the uniformity and precision of trench depths and widths, thereby enhancing the manufacturing process for stacked semiconductor devices.

Implementation Method 1

followed by thermal treatment to strengthen the bonds

Methodology Applied
Scientific EffectThermal treatment: Heat Treatment

Data Source

PatentUS20240128231A1Semiconductor Devices and Methods of Manufacture
Publication Date: 2024.04.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240128231A1 patent drawing
  • US20240128231A1 patent drawing
  • US20240128231A1 patent drawing

AI summary

Semiconductor devices and methods of manufacturing the semiconductor devices are presented. In embodiments the methods of manufacturing include depositing a first bonding layer on a first substrate, wherein the first substrate comprises a semiconductor substrate and a metallization layer. The first bonding layer and the semiconductor substrate are patterned to form first openings. A second substrate is bonded to the first substrate. After the bonding the second substrate, the second substrate is patterned to form second openings, at least one of the second openings exposing at least one of the first openings. After the patterning the second substrate, a third substrate is bonded to the second substrate, and after the bonding the third substrate, the third substrate is patterned to form third openings, at least one of the third openings exposing at least one of the second openings.