Stacked Semiconductor Package TSV Fault Detection and Repair
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Solution Overview
Problem
The complexity of 3D semiconductor packages with stacked silicon dies introduces challenges in die recovery, fault identification, and testing of Through Silicon Vias (TSVs), leading to high costs and yield losses due to defective TSVs, which cannot be efficiently repaired or tested without scrapping the entire device.
Innovation Solution
Implementing a system with redundant TSVs and a detour routing mechanism that allows for rerouting memory signal paths around faulty TSVs, along with a test port interface for identifying and repairing defective TSVs within the stacked die subsystems, enabling the reuse of otherwise faulty packages and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of repair
If redundant TSVs and detour routing mechanisms are implemented, then ease of repair is improved, but device complexity increases
Solution Approach 1:
The patent implements detour routing paths and redundant TSVs in advance during package fabrication, before any faults occur. These backup routing paths are pre-configured but remain inactive during normal operation. When a TSV fault is detected through the test port interface, the system activates the pre-prepared detour routing to bypass the defective TSV, enabling repair without scrapping the entire package.
Solution Approach 2:
The patent introduces a test port interface as an intermediary component that enables external testing and fault detection of TSVs. This test port serves as a mediator between the internal package structure and external testing equipment, allowing for non-destructive fault identification and facilitating the repair process without requiring complete package disassembly or destruction.
2Reliability
If comprehensive testing of TSVs is performed, then reliability is improved, but productivity decreases
Solution Approach 1:
The test port interface is integrated into the package structure during fabrication, preparing the testing infrastructure in advance. This allows for efficient fault detection later without requiring complex external modifications or time-consuming setup procedures, thereby minimizing the impact on manufacturing throughput while maintaining comprehensive testing capability.
3Ease of repair
If detour routing is implemented to bypass faulty TSVs, then ease of repair is improved, but manufacturing precision requirements increase
Solution Approach 1:
The detour routing paths are designed with local optimization, creating dedicated bypass routes that are spatially separated from the main TSV paths. This local quality approach allows the detour routes to be independently routed and connected, reducing the impact of alignment precision requirements on the overall package manufacturing while enabling effective fault bypass capability.
Data Source
AI summary
A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package. A plurality of Through Silicon Vias (TSVs) are formed through the two or more memory dies, wherein each of the plurality of TSVs traverse through the two or more memory layers to the functional silicon die via the WIO2 interface of the functional silicon die. A test port interface receives test signals from an external tester and routes the test signals through a steering logic communicably interfaced with the two or more memory dies. The steering logic shifts data into and out of the two or more memory dies through the plurality of TSVs.