3D Stacked Semiconductor Package with Through-Silicon Via Interconnects
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Solution Overview
Problem
Current semiconductor packages face challenges in efficiently connecting multiple upper semiconductor devices to a lower semiconductor device while maintaining a compact and lightweight design, especially in thin and ultrathin communication devices, where space and thickness are critical.
Innovation Solution
The semiconductor package design includes a lower package substrate with inner sides corresponding to upper package substrate sides, featuring upper semiconductor devices mounted near the outer sides, connected via lower chip connection elements that overlap and electrically connect with upper semiconductor devices, utilizing a metal core layer and interconnection layers for signal transmission, and independent channels for data and control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple upper semiconductor devices are connected to a lower semiconductor device using conventional methods, then electrical connection is achieved, but package thickness and complexity increase
Solution Approach 1:
The patent transitions from planar wire bonding to vertical through-silicon via (TSV) interconnections, moving electrical connections into the third dimension. Multiple upper semiconductor devices are connected to the lower device through vertical channels formed by TSVs, enabling dense stacking without increasing lateral footprint or excessive thickness. The TSV structure allows direct vertical electrical pathways through the substrate, resolving the contradiction between connection efficiency and package thickness.
Solution Approach 2:
The patent implements a nested package structure where upper semiconductor devices are stacked vertically on the lower device, with each layer containing multiple devices. The through-silicon via channels are nested within the substrate thickness, and multiple devices are nested in a vertical array. This nesting approach maximizes space utilization and enables efficient electrical connections between layers without proportionally increasing overall package thickness.
2Reliability
If multiple metal interconnection layers and wire bonding are used to connect upper and lower semiconductor devices, then reliable electrical connection is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts and eliminates the complex wire bonding process and multiple metal interconnection layers from the interconnection structure. Instead, it uses a simplified through-silicon via approach where copper-filled vias provide direct electrical pathways through the substrate. This extraction of unnecessary intermediate layers and processes reduces manufacturing complexity while maintaining connection reliability through the robust TSV structure.
Solution Approach 2:
The patent replaces the mechanical wire bonding process with a direct metallurgical connection through through-silicon vias. The electrical connection is achieved through copper-filled TSVs that are formed and filled using semiconductor fabrication processes rather than post-assembly wire bonding. This substitution eliminates the mechanical complexity of wire manipulation and bonding while providing more reliable electrical pathways.
3Ease of manufacture
If conventional package designs are used for communication devices, then manufacturing is straightforward, but the devices cannot achieve ultrathin and compact form factors
Solution Approach 1:
The patent adopts a three-dimensional stacked architecture with through-silicon via interconnections, moving from conventional two-dimensional planar packaging to vertical integration. This dimensional change enables ultrathin profile by stacking multiple semiconductor devices vertically, with electrical connections established through vertical TSV channels rather than lateral wire bonds. The approach maintains manufacturing feasibility using standard TSV fabrication processes while achieving the required thinness for portable devices.
Data Source
AI summary
Semiconductor packages are provided. The semiconductor packages may include an upper package including a plurality of upper semiconductor devices connected to an upper package substrate. The semiconductor packages may also include a lower package including a lower semiconductor device connected to a lower package substrate. The upper and lower packages may be connected to each other.