Stacked Semiconductor Package TSV Fault Recovery

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Solution Overview

Problem

The complexity of 3D semiconductor packages with stacked silicon dies introduces challenges in implementing die recovery, fault identification, and testing of Through Silicon Vias (TSVs) in Two-Level Memory (2LM) stacked die subsystems, leading to high costs and yield losses due to defective TSVs.

Innovation Solution

The implementation of redundant TSVs and re-routing schemes within the stacked semiconductor package allows for the rerouting of memory signal paths around defective TSVs, along with the use of test ports and DFX mechanisms for fault identification and testing, enabling the recovery of faulty packages and reducing scrap rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If 3D stacked semiconductor packages are implemented to increase circuit density and reduce physical space, then manufacturing precision and reliability are improved, but device complexity and difficulty of detecting faults increase

Engineering Contradiction:

Improvecircuit densityVSAvoidpackage structure

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the semiconductor package into multiple functional layers including a substrate, first semiconductor die, second semiconductor die, and third semiconductor die stacked vertically. Each layer contains specific circuitry and interconnection structures, allowing independent testing and fault isolation. The through-silicon vias (TSVs) are segmented into different functional groups (first TSVs for memory die connection, second TSVs for logic die connection) that can be tested separately.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary testing structure consisting of bump electrodes on the substrate that provide access points for external testing equipment. These bump electrodes serve as mediators between the external tester and the internal TSV structures, enabling non-destructive electrical testing of through-silicon vias without requiring physical disassembly of the stacked package.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If Through Silicon Vias (TSVs) are used to interconnect stacked dies, then manufacturing precision is improved, but reliability deteriorates due to defective TSVs causing high scrap rates

Engineering Contradiction:

Improvevia alignmentVSAvoidpackage yield

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent implements preliminary electrical testing of through-silicon vias using bump electrodes and external testing equipment before final package assembly. This allows defective TSVs to be identified and flagged early in the manufacturing process, enabling corrective actions such as rework or selective bypass routing before the package is completed and shipped, thereby improving overall yield.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the electrical parameters being tested by applying different test voltages and measuring corresponding currents through the TSVs via the bump electrodes. By varying test conditions and measuring electrical characteristics, the system can detect TSV defects that would not be apparent under normal operating conditions, improving defect detection capability without increasing physical complexity.

Inventive Principle:

Principle #35Parameter changes

3Ease of repair

If redundant TSVs and re-routing schemes are implemented to recover faulty packages, then ease of repair is improved, but device complexity increases

Engineering Contradiction:

Improvefault recoveryVSAvoidinterconnection structure

Core Design Contradiction:

Ease of repairVSDevice complexity

Solution Approach 1:

The patent incorporates redundant TSVs and alternative routing paths as a form of prior cushioning against potential TSV failures. During manufacturing, spare TSVs are prepared but not activated. If a TSV defect is detected during testing, the system can activate pre-configured alternative routes or redundant vias, allowing package recovery without requiring complex post-manufacturing repairs or complete package replacement.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent implements dynamic reconfiguration capability where the electrical connectivity of TSVs can be changed based on test results. Using the bump electrodes and control circuitry, the system can dynamically switch between different TSV configurations, activating redundant pathways only when needed. This maintains simplicity during normal operation while providing repair capability when faults are detected.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS9995785B2Stacked semiconductor package and method for performing bare die testing on a functional die in a stacked semiconductor package

Publication Date: 2018.06.12 TAHOE RES LTD

AI summary

Stacked semiconductor packages and methods for performing bare die testing on a functional silicon die in a stacked semiconductor package are described. In an example, a stacked semiconductor package includes a functional silicon die, a test controller having signature accumulation logic embedded therein, and a fabric to route transactions between the test controller and any of a plurality of near memory controllers of the functional silicon die.