Stacked Semiconductor Assembly for In-Process TSV Testing
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Solution Overview
Problem
Existing semiconductor manufacturing processes fail to effectively test the integrity of through-silicon vias (TSVs) until after the stacked semiconductor assembly is fully fabricated, leading to potential discarding of entire assemblies or devices due to undetected TSV failures.
Innovation Solution
The method involves flipping an end semiconductor die in the stack to enable backside bonding, allowing built-in test circuits to access and test all TSVs during assembly, using hybrid or solder bonding to create communicative couplings between pads and TSVs, and performing integrity checks throughout the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV integrity testing is performed after the stacked semiconductor assembly is fully fabricated, then the manufacturing process can be completed without interruption, but defective TSVs cannot be identified early leading to waste of entire assemblies
Solution Approach 1:
The patent applies preliminary action by performing TSV integrity testing during the stacking process before the assembly is complete. Test circuits are incorporated into the stack as it is being built, allowing TSV defects to be detected early in the fabrication process rather than after completion, thereby preventing waste of entire assemblies.
Solution Approach 2:
The patent uses an intermediary approach by introducing dedicated test circuits and test structures that mediate between the TSVs and testing equipment. These intermediary test structures enable indirect testing of TSV integrity through electrical connections that can be accessed during the stacking process without requiring complete assembly fabrication.
2Reliability
If functional tests are performed on semiconductor dies before assembly, then bad dies can be identified, but TSV integrity cannot be tested as the testing becomes complex and time consuming
Solution Approach 1:
The patent merges functional testing and TSV integrity testing into a unified testing approach. By incorporating TSV test circuits into the functional test infrastructure during the stacking process, the patent combines what were previously separate testing operations into a single integrated testing routine, reducing overall complexity.
Solution Approach 2:
The patent implements self-service by designing test circuits that automatically test TSV integrity as part of the normal stacking and assembly process. The test structures are configured to self-test without requiring external complex testing equipment or additional manual intervention, thereby simplifying the testing process.
3Productivity
If TSV testing is performed after assembly completion, then the manufacturing throughput is maintained, but the entire assembly must be discarded if TSV defects are found
Solution Approach 1:
The patent performs TSV testing as a preliminary action during the stacking process rather than after completion. This allows defective assemblies to be identified and removed early, preventing waste of good components that would otherwise be included in a complete assembly. The testing is integrated into the manufacturing flow to maintain throughput.
Solution Approach 2:
The patent implements feedback by using test results obtained during the stacking process to control subsequent manufacturing steps. If TSV defects are detected, the system provides feedback to stop further processing of that particular assembly, preventing waste of additional materials and components while maintaining overall manufacturing efficiency.
Data Source
AI summary
A stacked semiconductor device and methods for producing the same are disclosed here. A semiconductor device can include a first semiconductor die having a first backside passivation layer and a second semiconductor die having a second backside passivation layer. The first backside passivation layer interfaces to the second backside passivation layer to form a stacked semiconductor assembly and provide one or more communicative couplings between the first and second semiconductor dies. A method of forming a stacked semiconductor assembly includes aligning a first plurality of pads disposed in a first backside passivation layer of a first semiconductor die with a second plurality of pads disposed in a second backside passivation layer of a second semiconductor die. The method further includes bonding the first backside passivation layer to the second backside passivation layer to communicatively couple the first plurality of pads to the second plurality of pads.