Stacked Semiconductor Packages with Varying Underfill Materials
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor package industry faces challenges in miniaturization, lightweight design, and reliability due to increased failure rates when multiple semiconductor chips are packaged together, leading to reduced reliability and increased failure possibilities.
Innovation Solution
A semiconductor package design featuring multiple chips stacked with different horizontal widths and underfill layers made of varying materials, including adhesive materials and flowable liquid fill materials, with conductive contacts connected through electrodes, and a mold layer for enhanced adhesion and reduced contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are packaged within the same single semiconductor package, then integration and miniaturization are improved, but reliability is reduced and failure possibility increases
Solution Approach 1:
The patent divides the semiconductor package into multiple independent sub-packages, each housing a separate chip or chip stack. This segmentation isolates potential failures to individual sub-packages, preventing cascading failures across the entire package while maintaining high integration density through vertical stacking of multiple sub-packages.
Solution Approach 2:
The patent introduces an underfill layer as an intermediary substance between chips and substrates, and between different chip stacks. This underfill layer provides mechanical support, reduces stress, and improves thermal management, thereby enhancing the reliability of interconnections without compromising integration density.
2Volume of moving object
If multiple chips are stacked vertically to achieve miniaturization, then device size is reduced, but adhesion between chips becomes critical and failure risk increases
Solution Approach 1:
The underfill layer serves as a critical intermediary between stacked chips, providing mechanical bonding support and stress distribution. This layer ensures strong adhesion between chips while accommodating thermal expansion differences, enabling vertical stacking without compromising bond strength.
Solution Approach 2:
The patent employs composite material structures including the underfill layer composed of adhesive materials with specific mechanical and thermal properties. This composite approach combines materials with complementary characteristics to achieve both strong adhesion and thermal management in the vertically stacked configuration.
3Reliability
If different underfill layer materials are used between chips, then adhesion and reliability are improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies different underfill layer materials at different locations within the package based on specific requirements. For example, certain regions may use underfill with higher adhesive strength while other regions use materials optimized for thermal conductivity, allowing localized optimization without requiring complete redesign of the entire manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design minimizes failure and enhances reliability by improving adhesion between chips and reducing contact resistance, thereby increasing the overall performance and durability of the semiconductor package.
Implementation Method 1
a first underfill layer between the second semiconductor chip and the first semiconductor chip; a second underfill layer between the third semiconductor chip and the second semiconductor chip, and a third underfill layer between the fourth semiconductor chip and the third semiconductor chip
Implementation Method 2
the first and second semiconductor chips, the second and third semiconductor chips and the third and fourth semiconductor chips each have a plurality of corresponding conductive contacts that are in contact with each other, respectively
Data Source
AI summary
A semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a third semiconductor chip on the second semiconductor chip and a fourth semiconductor chip on the third semiconductor chip. A first underfill layer is positioned between the second semiconductor chip and the first semiconductor chip; a second underfill layer is positioned between the third semiconductor chip and the second semiconductor chip, and a third underfill layer is positioned between the fourth semiconductor chip and the third semiconductor chip. In some embodiments, the second underfill layer comprises a material that is different than the first and third underfill layers.