Stacked Semiconductor Package Signal Connection via Vias
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Solution Overview
Problem
In Package on Package (PoP) semiconductor packaging, temperature deviations cause deformation of the semiconductor substrate, leading to defects in solder joints due to differing thermal expansion coefficients between the upper and lower surfaces of stacked semiconductor packages.
Innovation Solution
A stack type semiconductor package apparatus with signal connection members, such as vias or sockets, are used to electrically connect semiconductor chips across packages, with conductive paste filled via holes and reflow processes ensuring secure connections, and redistribution layers on circuit boards to enhance conductivity and ease of stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder joints are used to electrically connect semiconductor packages in PoP structure, then electrical connection between packages is achieved, but deformation of semiconductor substrate due to thermal expansion coefficient differences causes solder joint defects
Solution Approach 1:
The patent introduces a signal connection member as an intermediary component between the first and second semiconductor packages. This signal connection member includes a first terminal electrode that contacts the upper surface of the first substrate and a second terminal electrode that contacts the lower surface of the second substrate, serving as a mediator to transmit signals while accommodating thermal expansion differences without directly relying on traditional solder joints between substrates
Solution Approach 2:
The patent segments the electrical connection path by introducing separate signal connection members for each connection point. Instead of relying on a continuous solder joint across the entire substrate interface, the connection is divided into discrete segments: first terminal electrode in first substrate, signal connection member, and second terminal electrode in second substrate, allowing independent movement and reducing stress concentration
2Productivity
If traditional PoP structure with direct substrate stacking is used, then compact vertical integration is achieved, but thermal expansion differences cause substrate deformation and irregular outer walls
Solution Approach 1:
The patent applies local quality by providing reinforcement structures at specific locations where thermal stress concentrates. The signal connection members are strategically positioned at locations requiring electrical connection, and reinforcement structures are added locally to maintain outer wall regularity in critical areas while preserving the overall compact vertical integration structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents defects in solder joints by maintaining stable connections across packages despite thermal expansion differences, improving conductivity and facilitating easy coupling and detachment of semiconductor packages.
Implementation Method 1
reflow processes ensuring secure connections
Data Source
AI summary
A semiconductor device includes a first semiconductor package having at least one first semiconductor chip and a first sealing member covering the at least one first semiconductor chip. The semiconductor device also includes a second semiconductor package stacked on the first semiconductor package. The second semiconductor package has at least one second semiconductor chip, leads electrically connected to the at least one second semiconductor chip, and a second sealing member covering the at least one second semiconductor chip. At least one signal connection member is disposed in the first sealing member of the first semiconductor package. The at least one signal connection member electrically connects the at least one first semiconductor chip with the leads of the at least one second semiconductor chip.